
;------------------------------------------------------------------------------
;  CHIP: SN8P2977, OTP Only.
;  Revision History:
;  V1.0  07/22/2016  First issue - Modified from SN8P2967
;		     !˘XDelet RomwrtVpp macro 

;------------------------------------------------------------------------------
.Assembly	INC_VER		1
.Assembly       RedWrt_FORMAT   1
.Assembly	ASM_FORMAT	1
.Assembly	RAM_Size	100h														

.Assembly	INSTRUMENT	SN8P2977
.Assembly	BIT_FILE	SN8P2977

.Assembly	OTP_BODY_SIZE	0x1000		
.Assembly	USER_ROM_SIZE	0x0FF8		

;.Assembly	COMMAND		Enable_ORG4_7, PullUp_P0, Enable_ISP		; Limit org 4~7, unavailible for user
.Assembly	COMMAND		Enable_ORG4_7, Enable_ISP
.Assembly	PGM_TYPE	6						; 2's Program Type			
.Assembly	MASK_TEST_CODE	0x0000, 0x000, 0x0000, 0x0000		
.Assembly	Port_Pins	8, 2, 8, 8, 0, 0, 0			
.Assembly	LCD_Size	16, 4							
.Assembly	CHIP_ID		0x9610					

; Code Option 0xFFF
.Assembly	OPTION			0		Fix_High	
.Assembly	OPTION			1		Security	Enable	Disable
.Assembly	OPTION			2		High_Clk_DIV	Fhosc/4 Fhosc/8 Fhosc/16 Fhosc/32 
.Assembly	OPTION			4 		High_Clk	IHRC	IHRC_RTC
.Assembly	OPTION			5 : 7		Fix_High 
.Assembly	OPTION			8		Watch_Dog	x x x x x Enable x x x x Disable x x x x Always_On 
.Assembly	OPTION			12 : 13		Fix_High			
.Assembly	OPTION			14		Low_Power	LP3 LP2 LP1 Normal 		

; Code Option 0xFFE
.Assembly	OPTION			16		Fix_Low
.Assembly	OPTION			17		Fix_High
.Assembly	OPTION			18		Fix_Low
.Assembly	OPTION			19		Fix_High
.Assembly	OPTION			20		Fix_High
.Assembly	OPTION			21		Fix_Low
.Assembly	OPTION			22		Fix_High
.Assembly	OPTION			23		Fix_Low
.Assembly	OPTION			24		Fix_Low
.Assembly	OPTION			25		Fix_High
.Assembly	OPTION			26		Fix_Low
.Assembly	OPTION			27 : 31		Fix_High

; Code Option 0xFFD
.Assembly	OPTION			32 : 40		Fix_High ;(IHRC_CAL_Data)
.Assembly	OPTION			41 : 47		Fix_High
;============================================================================
; Code Option 0xFFC
.Assembly	OPTION			48 : 63		Fix_High
.Assembly	OPTION			2ffh

	L			EQU		80h	
	H			EQU		81h
	R			EQU		82h
	Z			EQU		83h
	Y			EQU		84h
	
	PFLAG			EQU		86h
		FC		EQU		PFLAG.2
		FDC		EQU		PFLAG.1
		FZ		EQU		PFLAG.0
		
	RBANK			EQU		87h
		FRBNKS1		EQU		RBANK.1
		FRBNKS0		EQU		RBANK.0

	LCDM1			EQU		89h
		FLCDBNK		EQU		LCDM1.7
;				EQU		LCDM1.6
		FLCDMOD1	EQU		LCDM1.5
		FLCDMOD0	EQU		LCDM1.4
		FLCDEN		EQU		LCDM1.3
		FLCDBIAS	EQU		LCDM1.2		
		FLCDRATE	EQU		LCDM1.1
		FLCDCLK		EQU		LCDM1.0	

	LCDM2			EQU		8Ah
		FVAR1		EQU		LCDM2.7
		FVAR0		EQU		LCDM2.6
		FDISQ		EQU		LCDM2.5
;				EQU		LCDM2.4
		FVPPINTL	EQU		LCDM2.3	
		FVCP2		EQU		LCDM2.2		
		FVCP1		EQU		LCDM2.1
		FVCP0		EQU		LCDM2.0

	P2SEG			EQU		8Bh
		FP27SEG		EQU		P2SEG.7
		FP26SEG		EQU		P2SEG.6
		FP25SEG		EQU		P2SEG.5
		FP24SEG		EQU		P2SEG.4
		FP23SEG		EQU		P2SEG.3	
		FP22SEG		EQU		P2SEG.2		
		FP21SEG		EQU		P2SEG.1
		FP20SEG		EQU		P2SEG.0

	P3SEG			EQU		8Ch
		FP37SEG		EQU		P3SEG.7
		FP36SEG		EQU		P3SEG.6
		FP35SEG		EQU		P3SEG.5
		FP34SEG		EQU		P3SEG.4
		FP33SEG		EQU		P3SEG.3	
		FP32SEG		EQU		P3SEG.2		
		FP31SEG		EQU		P3SEG.1
		FP30SEG		EQU		P3SEG.0


	BZRM			EQU		8Dh
;				EQU		BZRM.7
;				EQU		BZRM.6
;				EQU		BZRM.5
;				EQU		BZRM.4
;				EQU		BZRM.3	
		FBZREN0		EQU		BZRM.2		
		FBZRCKS1	EQU		BZRM.1
		FBZRCKS0	EQU		BZRM.0




						
	VREG			EQU		90h
		FBGREN		EQU		VREG.7
		FBGCHP		EQU		VREG.6
		FAVEN		EQU		VREG.5
		FAVESEL1	EQU		VREG.4
		FAVESEL0	EQU		VREG.3
		FAVDDREN	EQU		VREG.2
		FAVDDRSEL1	EQU		VREG.1
		FAVDDRSEL0	EQU		VREG.0	


	CHS			EQU		91h
;				EQU		CHS.7
		FMUXP2		EQU		CHS.6
		FMUXP1		EQU		CHS.5
		FMUXP0		EQU		CHS.4
;				EQU		CHS.3
		FMUXN2		EQU		CHS.2
		FMUXN1		EQU		CHS.1
		FMUXN0		EQU		CHS.0	





	AMPM			EQU		92h
		FAMPCKS2	EQU		AMPM.7
		FAMPCKS1	EQU		AMPM.6
		FAMPCKS0	EQU		AMPM.5
		FPCHPEN		EQU		AMPM.4
		FGS2		EQU		AMPM.3
		FGS1		EQU		AMPM.2
		FGS0		EQU		AMPM.1
		FAMPEN		EQU		AMPM.0


		
	ADCM1			EQU		93h
		FRVS3		EQU		ADCM1.7
		FRVS2		EQU		ADCM1.6
		FRVS1		EQU		ADCM1.5
		FRVS0		EQU		ADCM1.4
		FACHPEN 	EQU		ADCM1.3
;				EQU		ADCM1.2
		FADGN		EQU		ADCM1.1
		FADCEN		EQU		ADCM1.0
				
	ADCM2			EQU		94h
		FADCKS		EQU		ADCM2.7
		FOSR2		EQU		ADCM2.6
		FOSR1		EQU		ADCM2.5
		FOSR0		EQU		ADCM2.4
;				EQU		ADCM2.3
		FOFSEL1		EQU		ADCM2.2
		FOFSEL0		EQU		ADCM2.1
		FDRDY		EQU		ADCM2.0

	LBTM			EQU		95h
;				EQU		LBTM.7
		FP11IO		EQU		LBTM.6
		FLBTSEL3	EQU		LBTM.5
		FLBTSEL2	EQU		LBTM.4
		FLBTSEL1	EQU		LBTM.3
		FLBTSEL0	EQU		LBTM.2
		FLBTO		EQU		LBTM.1
		FLBTEN		EQU		LBTM.0

	ADCDH			EQU_R		96h
	ADCDM			EQU_R		97h
	ADCDL			EQU_R		98h		
		
		
	ROMADRH			EQU		0A0h
		FROMADR15	EQU		ROMADRH.7
;				EQU		ROMADRH.6
;				EQU		ROMADRH.5
;				EQU		ROMADRH.4
		FROMADR11	EQU		ROMADRH.3
		FROMADR10	EQU		ROMADRH.2
		FROMADR9	EQU		ROMADRH.1
		FROMADR8	EQU		ROMADRH.0
			
	ROMADRL			EQU		0A1h	
		FROMADR7	EQU		ROMADRL.7
		FROMADR6	EQU		ROMADRL.6
		FROMADR5	EQU		ROMADRL.5
		FROMADR4	EQU		ROMADRL.4
		FROMADR3	EQU		ROMADRL.3
		FROMADR2	EQU		ROMADRL.2
		FROMADR1	EQU		ROMADRL.1
		FROMADR0	EQU		ROMADRL.0
	
	ROMDAH			EQU		0A2h
		FROMDA15	EQU		ROMDAH.7
		FROMDA14	EQU		ROMDAH.6
		FROMDA13	EQU		ROMDAH.5
		FROMDA12	EQU		ROMDAH.4
		FROMDA11	EQU		ROMDAH.3
		FROMDA10	EQU		ROMDAH.2
		FROMDA9		EQU		ROMDAH.1
		FROMDA8		EQU		ROMDAH.0

	ROMDAL			EQU		0A3h
		FROMDA7		EQU		ROMDAL.7
		FROMDA6		EQU		ROMDAL.6
		FROMDA5		EQU		ROMDAL.5
		FROMDA4		EQU		ROMDAL.4
		FROMDA3		EQU		ROMDAL.3
		FROMDA2		EQU		ROMDAL.2
		FROMDA1		EQU		ROMDAL.1
		FROMDA0		EQU		ROMDAL.0

	

	P0M			EQU		0B8h
		FP07M		EQU		P0M.7
		FP06M		EQU		P0M.6
		FP05M		EQU		P0M.5
		FP04M		EQU		P0M.4
		FP03M		EQU		P0M.3
		FP02M		EQU		P0M.2
		FP01M		EQU		P0M.1
		FP00M		EQU		P0M.0

	PEDGE			EQU		0BFh
;				EQU		PEDGE.7
		FP01G1		EQU		PEDGE.6
		FP01G0		EQU		PEDGE.5
		FP00G1		EQU		PEDGE.4
		FP00G0		EQU		PEDGE.3
;				EQU		PEDGE.2
;				EQU		PEDGE.1
;				EQU		PEDGE.0

	P1M			EQU		0C1h
		FP11M		EQU		P1M.1
		FP10M		EQU		P1M.0


	P2M			EQU		0C2h
		FP27M		EQU		P2M.7
		FP26M		EQU		P2M.6
		FP25M		EQU		P2M.5
		FP24M		EQU		P2M.4
		FP23M		EQU		P2M.3
		FP22M		EQU		P2M.2
		FP21M		EQU		P2M.1
		FP20M		EQU		P2M.0

	P3M			EQU		0C3h
		FP37M		EQU		P3M.7
		FP36M		EQU		P3M.6
		FP35M		EQU		P3M.5
		FP34M		EQU		P3M.4
		FP33M		EQU		P3M.3
		FP32M		EQU		P3M.2
		FP31M		EQU		P3M.1
		FP30M		EQU		P3M.0


	
	INTRQ			EQU		0C8H
		FADCIRQ		EQU		INTRQ.7
;				EQU		INTRQ.6		
		FTC0IRQ		EQU		INTRQ.5
		FT0IRQ		EQU		INTRQ.4
		FURXIRQ		EQU		INTRQ.3
		FUTXIRQ		EQU		INTRQ.2
		FP01IRQ		EQU		INTRQ.1			
		FP00IRQ		EQU		INTRQ.0

	INTEN			EQU		0C9H
		FADCIEN		EQU		INTEN.7
;				EQU		INTEN.6
		FTC0IEN		EQU		INTEN.5
		FT0IEN		EQU		INTEN.4
		FURXIEN		EQU		INTEN.3
		FUTXIEN		EQU		INTEN.2
		FP01IEN		EQU		INTEN.1		
		FP00IEN		EQU		INTEN.0

	OSCM			EQU		0CAh
		FCPUM1		EQU		OSCM.4
		FCPUM0		EQU		OSCM.3
		FCLKMD		EQU		OSCM.2
		FSTPHX		EQU		OSCM.1

	WDTR			EQU_W		0CCh	
	
	PCL			EQU		0CEh




	PCH			EQU		0CFH
;				EQU		PCH.7
;				EQU		PCH.6
;				EQU		PCH.5
;				EQU		PCH.4
		FPC11		EQU		PCH.3
		FPC10		EQU		PCH.2
		FPC9		EQU		PCH.1		
		FPC8		EQU		PCH.0




	P0			EQU		0D0H
		FP07		EQU		P0.7
		FP06		EQU		P0.6
		FP05		EQU		P0.5
		FP04		EQU		P0.4
		FP03		EQU		P0.3
		FP02		EQU		P0.2
		FP01		EQU		P0.1
		FP00		EQU		P0.0

	P1			EQU		0D1h
		FP11		EQU		P1.1
		FP10		EQU		P1.0


	P2			EQU		0D2H
		FP27		EQU		P2.7
		FP26		EQU		P2.6
		FP25		EQU		P2.5
		FP24		EQU		P2.4
		FP23		EQU		P2.3
		FP22		EQU		P2.2
		FP21		EQU		P2.1
		FP20		EQU		P2.0


	P3			EQU		0D3H
		FP37		EQU		P3.7
		FP36		EQU		P3.6
		FP35		EQU		P3.5
		FP34		EQU		P3.4
		FP33		EQU		P3.3
		FP32		EQU		P3.2
		FP31		EQU		P3.1
		FP30		EQU		P3.0





	T0M			EQU		0D8h
		FT0EN		EQU		T0M.7
		FT0RATE2	EQU		T0M.6
		FT0RATE1	EQU		T0M.5
		FT0RATE0	EQU		T0M.4
;				EQU		T0M.3
		FTC0X8		EQU		T0M.2
		FTC0GN		EQU		T0M.1
		FT0TB		EQU		T0M.0

	T0C			EQU		0D9h
	
	TC0M			EQU		0DAh
		FTC0EN		EQU		TC0M.7
		FTC0RATE2	EQU		TC0M.6
		FTC0RATE1	EQU		TC0M.5
		FTC0RATE0	EQU		TC0M.4
		FTC0CKS		EQU		TC0M.3
		FALOAD0		EQU		TC0M.2
		FTC0OUT		EQU		TC0M.1
		FPWM0OUT	EQU		TC0M.0
	
	TC0C			EQU		0DBH

	TC0R			EQU_W		0DCH		

	P2UR			EQU_W		0DDh
		FP27R		EQU_W		P2UR.7
		FP26R		EQU_W		P2UR.6
		FP25R		EQU_W		P2UR.5
		FP24R		EQU_W		P2UR.4
		FP23R		EQU_W		P2UR.3
		FP22R		EQU_W		P2UR.2
		FP21R		EQU_W		P2UR.1
		FP20R		EQU_W		P2UR.0


	P3UR			EQU_W		0DEh
		FP37R		EQU_W		P3UR.7
		FP36R		EQU_W		P3UR.6
		FP35R		EQU_W		P3UR.5
		FP34R		EQU_W		P3UR.4
		FP33R		EQU_W		P3UR.3
		FP32R		EQU_W		P3UR.2
		FP31R		EQU_W		P3UR.1
		FP30R		EQU_W		P3UR.0



	STKP			EQU		0DFh
		FGIE		EQU		STKP.7
		FSTKPB2		EQU		STKP.2
		FSTKPB1		EQU		STKP.1
		FSTKPB0		EQU		STKP.0

	P0UR			EQU_W		0E0h
		FP07R		EQU_W		P0UR.7
		FP06R		EQU_W		P0UR.6
		FP05R		EQU_W		P0UR.5
		FP04R		EQU_W		P0UR.4
		FP03R		EQU_W		P0UR.3
		FP02R		EQU_W		P0UR.2
		FP01R		EQU_W		P0UR.1
		FP00R		EQU_W		P0UR.0

	P1UR			EQU_W		0E1h
		FP11R		EQU_W		P1UR.1
		FP10R		EQU_W		P1UR.0
		
	URTX			EQU		0E2h
		FUTXEN		EQU		URTX.7		
		FUTXPEN		EQU		URTX.6
		FUTXPS		EQU		URTX.5
		FUTXBRK		EQU		URTX.4
		FURXBZ		EQU		URTX.3
		FUTXBZ		EQU		URTX.2
				
	URRX			EQU		0E3h
		FURXEN		EQU		URRX.7
		FURXPEN		EQU		URRX.6	
		FURXPS		EQU		URRX.5
		FURXPC		EQU		URRX.4
		FUFMER		EQU		URRX.3
		FURS2		EQU		URRX.2
		FURS1		EQU		URRX.1
		FURS0		EQU		URRX.0
	
	URCR			EQU		0E4h
	
	UTXD			EQU		0E5h

	URXD			EQU		0E6H
	




	@YZ			EQU		0E7h	

	@HL			EQU		0E8h	

	
	STK7L			EQU		0F0h
	STK7H			EQU		0F1h
	STK6L			EQU		0F2h
	STK6H			EQU		0F3h
	STK5L			EQU		0F4h
	STK5H			EQU		0F5h
	STK4L			EQU		0F6h
	STK4H			EQU		0F7h
	STK3L			EQU		0F8h
	STK3H			EQU		0F9h
	STK2L			EQU		0FAh
	STK2H			EQU		0FBh
	STK1L			EQU		0FCh
	STK1H			EQU		0FDh
	STK0L			EQU		0FEh
	STK0H			EQU		0FFh
	

; -----------------------------------------------------
; Clear watchdog macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2 

	@RST_WDT	macro		
 		   MOV  A, #0x5A
		   B0MOV  WDTR, A
	endm

; -----------------------------------------------------
; Sleep Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 1

	SleepMode	macro	
		B0BSET	FCPUM0
	endm

; -----------------------------------------------------
; Green Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 3

	GreenMode	macro	
		B0BSET	FCPUM1
		NOP
		NOP
	endm
	
; -----------------------------------------------------
; Slow Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2

	SLowMode	macro	
		B0BSET	FCLKMD
		B0BSET	FSTPHX
	endm

; -----------------------------------------------------
;  Slow mode to Normal Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 5

	Slow2Normal	macro	
		B0BCLR	FSTPHX
		NOP
		NOP
		NOP
		B0BCLR	FCLKMD
	endm
	



; -----------------------------------------------------
;  ISP ROM-Write with Internal VPP 7.5V Generation macro for compatibility in 2K Plus II ICE
;  Occupied Register: A,Y,Z,R  
;  execution time: 177ms
;  Output status: 

	RomwrtVpp 	macro
	local		ISPP_End,ISP_Delay10ms	

	;==== [ VPP Set 7.5V ] ===================
	MOV	A,#00100011b	; [ LCDBNK, -, LCDMOD1, LCDMOD0. LCDENB, LCDBIAS, LCDRATE, LCDCLK]
	XCH	a,LCDM1		; ChargePump start-up setting (ISP Mode, LCD Disable, 1/3 bias)
 	B0mov	Y,a		; Original setting of LCDM1 save in "Y" register

	;==== [ ISP Dlay 150ms wait VPP 7.5V stable ] ===================	
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 
	Call	ISP_Delay10ms	; for VPP 7.5V stable 


	Mov	a,#00001000b	; [ VAR1, VAR0, DISQ, -, VPPINTL, VCP2, VCP1, VCP0]
	XCH	a,LCDM2		; Set VCP=001 and VPPINTL=1. (VPP set 7.5V and VPP-VLCD short), others set default
	B0mov	z,a		; Original setting of LCDM2 save in "Z" register

	;==== [ ISP ROM Write Command ] ===========
	nop
	nop
	nop
	ROMWRT			; ISP ROM Write Instruction
	nop			; must nop

	b0bclr	FVPPINTL

	;==== [VLCD drop to 2.6V ] ================
	b0bclr	FLCDBIAS	; Set 1/3 Bias
	mov	a,#00100000b	;[ VAR1, VAR0, DISQ, x, VPPINTL, VCP2, VCP1, VCP0 ]
	b0mov	LCDM2,a		; VLCD discharge to VLCD=2.6V, VPPINTL=0

	;-- Delay 10ms ---------- 
	Call	ISP_Delay10ms

	b0bclr	FDISQ

	;===== [ Original LCD seting ] ============
	B0mov	a,z
	b0mov	LCDM2,a		
	B0mov	a,y
	b0mov	LCDM1,a
	jmp	ISPP_End

ISP_Delay10ms:
	;-- Delay 10ms -- 
	b0bset	FCLKMD	; Slow Mode
	NOP

	mov	a,#00
	add	a,#1
	cmprs	a,#18
	jmp	$-2
	
	b0bclr	FCLKMD	; Normal Mode	
ret
ISPP_End:
	endm


; ----------------------------------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------------------------------
;  ISP ROM-Write with Internal VPP 7.5V Generation macro for compatibility in 2K Plus II ICE
;  Occupied Register: A,Y,Z,R  
;  execution time: 177ms
;  Output status: 

	Temp_calibration 	macro	addr1,addr2,addr3
	local		Temp_calibration_END,ISP_command,ADC_Temp_set,ISP_Delay150ms_Temp,ISP_Delay10ms_Temp,Temp_error,clr_rdata_Temp_bit1,set_rdata_Temp_bit1,clr_rdata_Temp_bit0,bit_sent_routine,bit_sent_routine_function,bit_sent_routine_shift,Clr_command_bit1,Set_command_bit1,Clr_command_bit0,bit_accept_routine,bit_accept_routine_shift_1,bit_accept_routine_shift,Temp_change_addr_3,Temp_change_addr_2,Temp_change_addr,Temp_calibration_END_pr,Temp_DATA_to_59e90_2,Temp_addr_3,second_run_reload_TempAD,Start_reloat_float,Temp_DATA_to_59e90,Check_reload_data_method_1,Temp_addr_2,auto_temp_reload,ADC_Wait_Temp_isp,ROMADRL_PASS,Temp_convert_program,Temp_addr,Temp_value_isp_program,auto_temp_clication,selection_mode,state_command_3,state_command_2,state_selection,Password_command_bit0                                



	Call	ISP_Delay10ms_Temp
/*
	mov	a,#00H
	b0mov	P1,a
	mov	a,#0FFH
	b0mov	P1M,a
	b0mov	P1,a
	mov	a,#00H
	b0mov	P1,a
	mov	a,#0FFH
	b0mov	P1,a
*/
	mov	a,p0
	nop
	nop
	and	a,#00011110B
	cmprs	a,#00011000B
	jmp	Temp_calibration_END	


	;===== [ Compare Password ] ============

	;====test io=======
	/*
	mov	a,#00H
	b0mov	P1,a
	mov	a,#0FFH
	b0mov	P1M,a
	*/
	;==================
	mov	a,#00001000b
	b0mov	P0m,a

//	call	ADC_Temp_set




Password_command_bit0:

	call 	bit_accept_routine_shift

	;========select_mode==========

state_selection:
	b0bclr	P0.3
	Call	ISP_Delay10ms_Temp
	b0bset	P0.3
	b0mov	a,Y
	cmprs	a,#5AH
	jmp	state_command_2
	mov	a,#00H
	jmp	selection_mode		

state_command_2:
	b0mov	a,Y
	cmprs	a,#0A5H
	jmp	state_command_3
	mov	a,#01H
	jmp	selection_mode	

state_command_3:
	;========Reseved==========
	jmp	Temp_calibration_END	

selection_mode:
	b0add	PCL,a
	jmp	auto_temp_clication
	jmp	auto_temp_reload	



auto_temp_clication:
	;===== [ Set Temp_AD Convertor] ============
	//call	ADC_Temp_set
	;===== [ Accept Temp and program this value by isp] ============

	call bit_accept_routine_shift
	b0mov	A,Y
	b0mov	ROMDAH,A
	call bit_accept_routine_shift
	b0mov	A,Y
	b0mov	ROMDAL,A



Temp_value_isp_program:

	;==== [ Check & set address ] ===================
/*
	B0MOV	Z, #00H
//	B0MOV	Y, #0FH
	B0MOV	Y, #07H
*/

	MOV	A,addr2
	B0MOV	Z,A
	MOV	A,addr1
	B0MOV	Y,A

Temp_addr:
	MOVC	
	CMPRS	A,#0FFH
	JMP	Temp_change_addr
	B0MOV	A, R	
	CMPRS	A,#0FFH	
	JMP	Temp_change_addr
	B0MOV	A,Z
	B0MOV	ROMADRL, A		;Move Low Byte Address to ROMADRL
	B0MOV	A,Y
	B0MOV	ROMADRH, A		;Move High Byte Address to ROMADRH

	CALL	ISP_command
	
	MOV	a,#00H
	B0MOV	R,A

Temp_convert_program:
	;===== [ Set Temp_AD Convertor] ============
	call	ADC_Temp_set
	CALL	ISP_Delay150ms_Temp	
	CALL	ISP_Delay150ms_Temp
	CALL	ISP_Delay150ms_Temp

	;===== [ Program Temp ADC Code ] ============
	INCMS	ROMADRL
	JMP	ROMADRL_PASS
	JMP	Temp_error
ROMADRL_PASS:	
	B0BCLR	FDRDY
ADC_Wait_Temp_isp:
	B0BTS1	FDRDY		;ADC Conversion Ready bit
	JMP	ADC_Wait_Temp_isp
	B0BCLR	FDRDY
	;===== [ FOR "Temp_convert_output" FUNCTION  ] ============	
	B0MOV	A,R
	CMPRS	A,#00h
	RET
	;==========================================================
	B0MOV	A,ADCDH
	B0MOV	ROMDAH,A		
	B0MOV	A,ADCDM
	B0MOV	ROMDAL,A	

	call	ISP_command


auto_temp_reload:
	b0bset	P0M.1
	b0bset	P0M.2	

	;==== [ Check_method_1:check from end addr ] ===================
/*
	B0MOV	Z, #50H
//	B0MOV	Y, #0FH
	B0MOV	Y, #07H
*/

	MOV	A,addr3	
	B0MOV	Z,A
	MOV	A,addr1
	B0MOV	Y,A


	;==== [ Check & set address ] ===================
/*
	;==== [ Check_method_2:check from start addr ] ===================	
	B0MOV	Z, #00H
	B0MOV	Y, #07H
*/
Temp_addr_2:
	MOVC	
	;==== [ Check_method_1:check from end addr ] ===================
	CMPRS	A,#0FFH
	JMP	Check_reload_data_method_1
	B0MOV	A, R	
	CMPRS	A,#0FFH	
	JMP	Check_reload_data_method_1
	JMP	Temp_change_addr_2	




Check_reload_data_method_1:
//	DECMS	Z			;if the Z=1,this condition will fail
//	JMP	Temp_DATA_to_59e90
//	JMP	Temp_error
	b0mov	a,Z
	SUB	a,#01H
	b0mov	Z,a

	
	
;========Temp_Data_to_sh59e90========
Temp_DATA_to_59e90:
	MOVC
	B0MOV	Z,A
	B0MOV	A,R
	B0MOV	Y,A
	;------init R=0 to determine that float_A was ended by R=1 -------
	MOV	A,#00H
	B0MOV	R,A
	;-----------------------------------------------------------------
Start_reloat_float:	
	CALL	bit_sent_routine_shift
	MOV	A,Z
	b0mov	Y,A
	CALL	bit_sent_routine_shift




second_run_reload_TempAD:
	b0mov	a,R
	cmprs	a,#00H
	jmp	Temp_calibration_END_pr
	;==== [ Check_method:check from end addr ] ===================
/*
	B0MOV	Z, #50H
//	B0MOV	Y, #0FH
	B0MOV	Y, #07H
*/

	MOV	A,addr3	
	B0MOV	Z,A
	MOV	A,addr1
	B0MOV	Y,A

	;==== [ Check & set address ] ===================
Temp_addr_3:
	MOVC	
	;==== [ Check_method:check from end addr ] ===================
	CMPRS	A,#0FFH
	JMP	Temp_DATA_to_59e90_2
	B0MOV	A, R	
	CMPRS	A,#0FFH	
	JMP	Temp_DATA_to_59e90_2
	JMP	Temp_change_addr_3

Temp_DATA_to_59e90_2:
	MOVC
	B0MOV	Z,A
	B0MOV	A,R
	B0MOV	Y,A
	;------init R=0 to determine that float_A was ended by R=1 -------
	MOV	A,#01H
	B0MOV	R,A
/*
	b0bclr	P0.3
	Call	ISP_Delay10ms_Temp	
	b0bset	P0.3
*/
	jmp	Start_reloat_float


Temp_calibration_END_pr:
/*
	b0bclr	P0.3
	Call	ISP_Delay10ms_Temp	
	b0bset	P0.3
*/
	JMP	Temp_calibration_END



Temp_change_addr:
	INCMS	Z
	JMP	Temp_addr
	JMP	Temp_error	

Temp_change_addr_2:
	;==== [ Check_method:check from end addr ] ===================
	DECMS	Z
	JMP	Temp_addr_2
	JMP	Temp_error
Temp_change_addr_3:
	;==== [ Check_method:check from end addr ] ===================
	DECMS	Z
	JMP	Temp_addr_3
	JMP	Temp_error



;============ [ Accept_data_function ] ===================
bit_accept_routine_shift:
	mov	a,#00H
	b0mov	Y,a
	b0mov	Z,a
	b0mov	R,a	
bit_accept_routine_shift_1:
	b0bclr	P0.3
	call 	bit_accept_routine
	RLCM	Y
	RLCM	Y
	RLCM	Y
	RLCM	Y
	RLCM	Y
	RLCM	Y
	MOV	A,#11000000b
	AND	A,Y
	OR	R,A
	b0bset	P0.3
	call 	bit_accept_routine
	RLCM	Y
	RLCM	Y
	RLCM	Y
	RLCM	Y
	MOV	A,#00110000b
	AND	A,Y
	OR	R,A
	b0bclr	P0.3
	call 	bit_accept_routine
	RLCM	Y
	RLCM	Y
	MOV	A,#00001100b
	AND	A,Y
	OR	R,A
	b0bset	P0.3
	call 	bit_accept_routine
	MOV	A,#00000011b
	AND	A,Y
	OR	R,A
	b0mov	A,R
	b0mov	Y,A
ret

bit_accept_routine:
//	b0bclr	P0.3
	Call	ISP_Delay10ms_Temp
	b0mov	a,P0
	and	a,#00000010B
	cmprs	a,#00000010B
	jmp	Clr_command_bit0
	b0bset	Y.0
	jmp	Set_command_bit1
Clr_command_bit0:
	b0bclr	Y.0

Set_command_bit1:
	b0mov	a,P0
	and	a,#00000100B
	cmprs	a,#00000100B
	jmp	Clr_command_bit1
	b0bset	Y.1
	ret

Clr_command_bit1:
	b0bclr	Y.1


ret
	
;=======================================================


;============ [ Sent_data_function ] ===================
bit_sent_routine_shift:
	
	
	call	bit_sent_routine
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	b0bclr	P0.3
	call	bit_sent_routine_function
/*
	Call	ISP_Delay10ms_Temp
	RRCM	Y
	RRCM	Y
	call	bit_sent_routine
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
*/
	b0bset	P0.3
	call	bit_sent_routine_function
	b0bclr	P0.3
	call	bit_sent_routine_function
	b0bset	P0.3
	Call	ISP_Delay10ms_Temp


ret

bit_sent_routine_function:
	Call	ISP_Delay10ms_Temp
	RRCM	Y
	RRCM	Y
	call	bit_sent_routine
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp

ret


bit_sent_routine:
	B0MOV	A,Y
	AND	A,#00000001B
	cmprs	a,#00000001B
	jmp	clr_rdata_Temp_bit0
	b0bset	P0.1
	jmp	set_rdata_Temp_bit1
clr_rdata_Temp_bit0:
	b0bclr	P0.1
	
set_rdata_Temp_bit1:
	B0MOV	A,Y
	AND	A,#00000010B
	cmprs	a,#00000010B
	jmp	clr_rdata_Temp_bit1
	b0bset	P0.2
	ret
clr_rdata_Temp_bit1:
	b0bclr	P0.2

ret
;=======================================================

Temp_error:
	b0bset	P0M.4
	b0bclr	P0.4
	JMP	$

ISP_Delay10ms_Temp:
	;-- Delay 10ms -- 
	b0bset	FCLKMD	; Slow Mode
	NOP

	mov	a,#00
	add	a,#1
	cmprs	a,#18
	jmp	$-2
	
	b0bclr	FCLKMD	; Normal Mode	
ret



ISP_Delay150ms_Temp:

	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	Call	ISP_Delay10ms_Temp
	
ret

ADC_Temp_set:
/*
	;===== [ Setting ADC_Temp ] ============

	;===== [ CPREG_Init ] ============
	B0BSET	FBGREN		; Enable Band Gap Reference voltage
;	B0BCLR	FBGREN		; Disable Band Gap Reference voltage	

	;===== [ AVDDR_Selection ] ============
;	B0BSET	FAVDDRENS	; Enable AVDDR Slow Turn On Output voltage. (@CR2032 Battery Case)
;	B0BCLR	FAVDDRENS	; AVDDR Normal Turn On Output voltage.

	;===== [ AVDDR_Enable ] ============
	B0BCLR	FAVDDRSEL1	; Set AVDDR output 2.4V ,AVDDRSEL[1:0]:01 = AVDDR 2.4V.
	B0BSET	FAVDDRSEL0	; Set AVDDR output 2.4V

	B0BSET	FAVDDREN	; Enable Regulator and AVDDR Output voltage

	;===== [ PGIA_Init ] ============
	MOV	A, #10101000B	; PGIA channel (Temperature sensor) and PGIA Gain x 1
	B0MOV	AMPM1, A	
	MOV	A, #00011100B 	;PGIA Chopper frequency enable amd PGIA chopper frequency selection(31.25KHz@ADC_CLK=250k)
	B0MOV	AMPM2, A	
	B0BSET	FAMPEN		; Enable PGIA function
				

	;===== [ ADC_Init ] ============
	MOV	A, #01000000B	;ADC Internal Reference Voltage(0.84V@AVDDR=2.4V)
	B0MOV	ADCM1, A	
 	B0BSET	FACHPEN		;ADC Chopper Enable
;	MOV	A, #01110110B	;ADC OSR Select 32768 and ADC Offset Slect 00% Vref
	MOV	A, #01000110B	;ADC OSR Select 4096 and ADC Offset Slect 00% Vref		
	B0MOV	ADCM2, A
;	B0BSET	FADCKS		;ADC clock source set 333kHz	
	B0BSET	FADCEN
*/
	;***********[Channel selection]*********************************
;	mov	a,#00000001B		;AI1/AI2	
;	mov	a,#00100011B		;AI3/AI4	
;	mov	a,#01010101B		;VDD_DET
	mov	a,#01100110B		;Temp
	mov	CHS,a
	;***********[Regulator setting]*********************************	
;	mov	a,#10111100b		;AVE=2VˇBAVDDR=2.2V
	mov	a,#10111101b		;AVE=2VˇBAVDDR=2.4V
;	mov	a,#10111110b		;AVE=2VˇBAVDDR=2.8V
;	mov	a,#10111111b		;AVE=2VˇBAVDDR=3.2V
;	mov	a,#10110100b		;AVE=1.5VˇBAVDDR=2.2V
;	mov	a,#10110101b		;AVE=1.5VˇBAVDDR=2.4V
;	mov	a,#10110110b		;AVE=1.5VˇBAVDDR=2.8V
;	mov	a,#10110111b		;AVE=1.5VˇBAVDDR=3.2V
	b0mov	VREG,a
	;***********[PGIA setting]**************************************	
;	mov	a,#00000111b
;	b0mov	AMPM1,a
;	mov	a,#00011100b
;	b0mov	AMPM2,a

;	mov	a,#00011101b

	mov	a,#00010000b		;Chopper=31.25KˇB Disable PGIA function. (PGIA input signal by pass to ADC)
;	mov	a,#00010001b		;Chopper=31.25KˇBPGIA=1x
;	mov	a,#00010011b		;Chopper=31.25KˇBPGIA=4x
;	mov	a,#00010101b		;Chopper=31.25KˇBPGIA=8x
;	mov	a,#00010111b		;Chopper=31.25KˇBPGIA=16x
;	mov	a,#00011001b		;Chopper=31.25KˇBPGIA=32x
;	mov	a,#00011011b		;Chopper=31.25KˇBPGIA=64x
;	mov	a,#00011101b		;Chopper=31.25KˇBPGIA=128x
;	mov	a,#00011111b		;Chopper=31.25KˇBPGIA=192x

	b0mov	AMPM,a	
	;**********[ADC setting]*****************************************	
;	mov	a,#01001001b		;ADC_G=1xˇBVref=0.36v
;	mov	a,#01011001b		;ADC_G=1xˇBVref=0.6v
;	mov	a,#01101001b		;ADC_G=1xˇBVref=0.84v
;	mov	a,#01111001b		;ADC_G=1xˇBVref=1.2v
;	mov	a,#01001011b		;ADC_G=2xˇBVref=0.36v
;	mov	a,#01011011b		;ADC_G=2xˇBVref=0.6v
;	mov	a,#01101011b		;ADC_G=2xˇBVref=0.84v
;	mov	a,#01111011b		;ADC_G=2xˇBVref=1.2v
	mov	a,#10001001b		;ADC_G=1xˇBVref=0.8VBG
	b0mov	ADCM1,a

	mov	a,#01000110b		;OSR=4096ˇBOFFset=0*Vref
;	mov	a,#01110110b		;OSR=32768ˇBOFFset=0*Vref
;	mov	a,#00100100b		;OSR=256ˇBOFFset=-1/4*Vref
;	mov	a,#00100010b		;OSR=256ˇBOFFset=-1/2*Vref
;	mov	a,#00100000b		;OSR=256ˇBOFFset=-3/4*Vref
	b0mov	ADCM2,a
ret


ISP_command:
	;==== [ VPP Set 7.5V ] ===================
	MOV	A,#00100011b	; [ LCDBNK, -, LCDMOD1, LCDMOD0. LCDENB, LCDBIAS, LCDRATE, LCDCLK]
	XCH	a,LCDM1		; ChargePump start-up setting (ISP Mode, LCD Disable, 1/3 bias)
 	B0mov	Y,a		; Original setting of LCDM1 save in "Y" register

	;==== [ ISP Dlay 150ms wait VPP 7.5V stable ] ===================	

	CALL	ISP_Delay150ms_Temp

	Mov	a,#00001000b	; [ VAR1, VAR0, DISQ, -, VPPINTL, VCP2, VCP1, VCP0]
	XCH	a,LCDM2		; Set VCP=001 and VPPINTL=1. (VPP set 7.5V and VPP-VLCD short), others set default
	B0mov	z,a		; Original setting of LCDM2 save in "Z" register

	;==== [ ISP ROM Write Command ] ===========
	nop
	nop
	nop
	ROMWRT			; ISP ROM Write Instruction
	nop			; must nop

	b0bclr	FVPPINTL


	;==== [VLCD drop to 2.6V ] ================
	b0bclr	FLCDBIAS	; Set 1/3 Bias
	mov	a,#00100000b	;[ VAR1, VAR0, DISQ, x, VPPINTL, VCP2, VCP1, VCP0 ]
	b0mov	LCDM2,a		; VLCD discharge to VLCD=2.6V, VPPINTL=0

	;-- Delay 10ms ---------- 
	Call	ISP_Delay10ms_Temp

	b0bclr	FDISQ


	;===== [ Original LCD seting ] ============
	B0mov	a,z
	b0mov	LCDM2,a		
	B0mov	a,y
	b0mov	LCDM1,a
ret


/*
Temp_convert_output:
	call	ADC_Temp_set
	;==== [ Check from end addr ] ===================
	B0MOV	Z, #50H
//	B0MOV	Y, #0FH
	B0MOV	Y, #07H
Temp_out_addr_Check:
	MOVC	
	;==== [ Check_method_1:check from end addr ] ===================
	CMPRS	A,#0FFH
	JMP	Check_reload_data_method_1
	B0MOV	A, R	
	CMPRS	A,#0FFH	
	JMP	Check_reload_data_method_1
	DECMS	Z
	JMP	Temp_out_addr_Check	

;	b0mov	a,Z
;	SUB	a,#01H
;	b0mov	Z,a

	MOV	A,#01H
	B0MOV	R,A
	
	CALL	Temp_convert_program

	MOVC
	B0MOV	Z,A
	B0MOV	A,R
	B0MOV	Y,A


	MOV	A,ADCDM
	SUB	A,Z
	B0MOV	Z,A
	MOV	A,ADCDH
	SBC	A,Y
	B0MOV	Y,A	





	
ret

*/


Temp_calibration_END:
;	mov	a,#0FFH
;	b0mov	P1,a
//	jmp	main
//	jmp	main_loop
/*
org	0x700
RAM_TAB:
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 
  DW 00FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH 0FFFFH
*/


	endm

; -----------------------------------------------------	
.TEXT
{
	//{{SONIX_OPTION_RULE
        
	ENDP
	//}}SONIX_OPTION_RULE
}