Electric can produce input decks for Verilog simulation with Write Verilog Deck... command (in menu Tools / Simulation (Verilog)). After this has been done, you must run Verilog externally to produce a ".dump" file. Note that the Electric distribution does not come with a Verilog simulator: you must obtain it separately.

After running a Verilog simulation, you can read the ".dump" file into Electric and display it in a waveform window. This is done with the Plot Verilog VCD Dump... command (in menu Tools / Simulation (Verilog)). You can also use the Plot Verilog for This Cell command if the cell name and file name are the same. The Verilog simulation information is then shown in a digital waveform window (see Section 4-11-1 for more). Electric also understands the output of Modelsim and can plot it.

Before generating Verilog decks, it is possible to annotate circuits with additional Verilog text that will be included in the deck. To add Verilog code to this cell, select "Verilog Code" under the "Misc." entry in the component menu of the side bar. To add a Verilog declaration in this cell, select "Verilog Declaration" under the "Misc." entry in the component menu. To add a Verilog parameter to this cell, select "Verilog Parameter" under the "Misc." entry in the component menu. To add external Verilog code, outside of this cell, select "Verilog External Code" under the "Misc." entry in the component menu. These pieces of text can be manipulated like any other text object (see Section 6-8-1 on text). For an example of Verilog layout and code, look at the cell "tool-SimulateVERILOG" in the Samples library (get this library with the Load Sample Cells Library command, in menu Help).

Additional control of Verilog deck generation is accomplished with the Verilog Preferences (in menu File / Preferences..., "Tools" section, "Verilog" tab).

The left side is the Verilog Project Preferences which has two controls:

- "Use ASSIGN Construct" lets you choose whether or not to use the Verilog "assign" construct.
- "Default wire is Trireg" lets you control the type of Verilog declaration that will be used for wires ("wire" by default, "trireg" if checked). Note that this can be overridden with the Set Verilog Wire command (in menu Tools / Simulation (Verilog)).

Another property that can be assigned to transistors is their strength. The Weak command (in menu Tools / Simulation (Verilog) / Transistor Strength) sets the transistor to be weak. The Normal command restores the transistor to be normal strength.

Still more control of Verilog deck generation is accomplished with the Verilog User Preferences in the right side of the dialog.

- "Do not netlist Standard Cells" writes a netlist that excludes Standard Cells. Any cell marked as a Standard Cell will be netlisted only as instances, but no module definition will be written. This allows Standard Cell based simulation or Static Timing Analysis to be performed on the netlist. See Section 3-7-3 for more on marking cells as "standard cells".
- "Preserve Verilog formatting" keeps the indentation and other formatting of all inserted text.
- "Parameterize Verilog module names" causes Verilog deck generation to create multiple Verilog cell descriptions when the cells are parameterized.

A final set of Verilog controls can be found in the Verilog Model Files Preferences (in menu File / Preferences..., "Tools" section, "Verilog Model Files" tab). The Verilog Model Files Preferences dialog lets you attach disk files with Verilog code to any cell in the library.

Once attached, the generated Verilog will use the contents of that file instead of examining the cell contents. This allows you to create your own definitions in situations where the derived Verilog would be too complex or otherwise incorrect. |