
demo.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00000122  00000000  00000000  00000074  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .bss          00000003  00800060  00800060  00000196  2**0
                  ALLOC
  2 .debug_aranges 00000020  00000000  00000000  00000196  2**0
                  CONTENTS, READONLY, DEBUGGING
  3 .debug_pubnames 00000035  00000000  00000000  000001b6  2**0
                  CONTENTS, READONLY, DEBUGGING
  4 .debug_info   00000105  00000000  00000000  000001eb  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_abbrev 000000cf  00000000  00000000  000002f0  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_line   00000171  00000000  00000000  000003bf  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_frame  00000040  00000000  00000000  00000530  2**2
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_str    000000cc  00000000  00000000  00000570  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	12 c0       	rjmp	.+36     	; 0x26 <__ctors_end>
   2:	2c c0       	rjmp	.+88     	; 0x5c <__bad_interrupt>
   4:	2b c0       	rjmp	.+86     	; 0x5c <__bad_interrupt>
   6:	2a c0       	rjmp	.+84     	; 0x5c <__bad_interrupt>
   8:	29 c0       	rjmp	.+82     	; 0x5c <__bad_interrupt>
   a:	28 c0       	rjmp	.+80     	; 0x5c <__bad_interrupt>
   c:	27 c0       	rjmp	.+78     	; 0x5c <__bad_interrupt>
   e:	26 c0       	rjmp	.+76     	; 0x5c <__bad_interrupt>
  10:	26 c0       	rjmp	.+76     	; 0x5e <__vector_8>
  12:	24 c0       	rjmp	.+72     	; 0x5c <__bad_interrupt>
  14:	23 c0       	rjmp	.+70     	; 0x5c <__bad_interrupt>
  16:	22 c0       	rjmp	.+68     	; 0x5c <__bad_interrupt>
  18:	21 c0       	rjmp	.+66     	; 0x5c <__bad_interrupt>
  1a:	20 c0       	rjmp	.+64     	; 0x5c <__bad_interrupt>
  1c:	1f c0       	rjmp	.+62     	; 0x5c <__bad_interrupt>
  1e:	1e c0       	rjmp	.+60     	; 0x5c <__bad_interrupt>
  20:	1d c0       	rjmp	.+58     	; 0x5c <__bad_interrupt>
  22:	1c c0       	rjmp	.+56     	; 0x5c <__bad_interrupt>
  24:	1b c0       	rjmp	.+54     	; 0x5c <__bad_interrupt>

00000026 <__ctors_end>:
  26:	11 24       	eor	r1, r1
  28:	1f be       	out	0x3f, r1	; 63
  2a:	cf e5       	ldi	r28, 0x5F	; 95
  2c:	d4 e0       	ldi	r29, 0x04	; 4
  2e:	de bf       	out	0x3e, r29	; 62
  30:	cd bf       	out	0x3d, r28	; 61

00000032 <__do_copy_data>:
  32:	10 e0       	ldi	r17, 0x00	; 0
  34:	a0 e6       	ldi	r26, 0x60	; 96
  36:	b0 e0       	ldi	r27, 0x00	; 0
  38:	e2 e2       	ldi	r30, 0x22	; 34
  3a:	f1 e0       	ldi	r31, 0x01	; 1
  3c:	02 c0       	rjmp	.+4      	; 0x42 <.do_copy_data_start>

0000003e <.do_copy_data_loop>:
  3e:	05 90       	lpm	r0, Z+
  40:	0d 92       	st	X+, r0

00000042 <.do_copy_data_start>:
  42:	a0 36       	cpi	r26, 0x60	; 96
  44:	b1 07       	cpc	r27, r17
  46:	d9 f7       	brne	.-10     	; 0x3e <.do_copy_data_loop>

00000048 <__do_clear_bss>:
  48:	10 e0       	ldi	r17, 0x00	; 0
  4a:	a0 e6       	ldi	r26, 0x60	; 96
  4c:	b0 e0       	ldi	r27, 0x00	; 0
  4e:	01 c0       	rjmp	.+2      	; 0x52 <.do_clear_bss_start>

00000050 <.do_clear_bss_loop>:
  50:	1d 92       	st	X+, r1

00000052 <.do_clear_bss_start>:
  52:	a3 36       	cpi	r26, 0x63	; 99
  54:	b1 07       	cpc	r27, r17
  56:	e1 f7       	brne	.-8      	; 0x50 <.do_clear_bss_loop>
  58:	4e d0       	rcall	.+156    	; 0xf6 <main>
  5a:	61 c0       	rjmp	.+194    	; 0x11e <_exit>

0000005c <__bad_interrupt>:
  5c:	d1 cf       	rjmp	.-94     	; 0x0 <__vectors>

0000005e <__vector_8>:
#include "iocompat.h"		/* Note [1] */

enum { UP, DOWN };

ISR (TIMER1_OVF_vect)		/* Note [2] */
{
  5e:	1f 92       	push	r1
  60:	0f 92       	push	r0
  62:	0f b6       	in	r0, 0x3f	; 63
  64:	0f 92       	push	r0
  66:	11 24       	eor	r1, r1
  68:	2f 93       	push	r18
  6a:	3f 93       	push	r19
  6c:	8f 93       	push	r24
    static uint16_t pwm;	/* Note [3] */
    static uint8_t direction;

    switch (direction)		/* Note [4] */
  6e:	80 91 60 00 	lds	r24, 0x0060
  72:	88 23       	and	r24, r24
  74:	c1 f4       	brne	.+48     	; 0xa6 <__vector_8+0x48>
    {
        case UP:
            if (++pwm == TIMER1_TOP)
  76:	20 91 61 00 	lds	r18, 0x0061
  7a:	30 91 62 00 	lds	r19, 0x0062
  7e:	2f 5f       	subi	r18, 0xFF	; 255
  80:	3f 4f       	sbci	r19, 0xFF	; 255
  82:	30 93 62 00 	sts	0x0062, r19
  86:	20 93 61 00 	sts	0x0061, r18
  8a:	83 e0       	ldi	r24, 0x03	; 3
  8c:	2f 3f       	cpi	r18, 0xFF	; 255
  8e:	38 07       	cpc	r19, r24
  90:	09 f1       	breq	.+66     	; 0xd4 <__vector_8+0x76>
            if (--pwm == 0)
                direction = UP;
            break;
    }

    OCR = pwm;			/* Note [5] */
  92:	3b bd       	out	0x2b, r19	; 43
  94:	2a bd       	out	0x2a, r18	; 42
}
  96:	8f 91       	pop	r24
  98:	3f 91       	pop	r19
  9a:	2f 91       	pop	r18
  9c:	0f 90       	pop	r0
  9e:	0f be       	out	0x3f, r0	; 63
  a0:	0f 90       	pop	r0
  a2:	1f 90       	pop	r1
  a4:	18 95       	reti
ISR (TIMER1_OVF_vect)		/* Note [2] */
{
    static uint16_t pwm;	/* Note [3] */
    static uint8_t direction;

    switch (direction)		/* Note [4] */
  a6:	81 30       	cpi	r24, 0x01	; 1
  a8:	29 f0       	breq	.+10     	; 0xb4 <__vector_8+0x56>
  aa:	20 91 61 00 	lds	r18, 0x0061
  ae:	30 91 62 00 	lds	r19, 0x0062
  b2:	ef cf       	rjmp	.-34     	; 0x92 <__vector_8+0x34>
            if (++pwm == TIMER1_TOP)
                direction = DOWN;
            break;

        case DOWN:
            if (--pwm == 0)
  b4:	20 91 61 00 	lds	r18, 0x0061
  b8:	30 91 62 00 	lds	r19, 0x0062
  bc:	21 50       	subi	r18, 0x01	; 1
  be:	30 40       	sbci	r19, 0x00	; 0
  c0:	30 93 62 00 	sts	0x0062, r19
  c4:	20 93 61 00 	sts	0x0061, r18
  c8:	21 15       	cp	r18, r1
  ca:	31 05       	cpc	r19, r1
  cc:	11 f7       	brne	.-60     	; 0x92 <__vector_8+0x34>
                direction = UP;
  ce:	10 92 60 00 	sts	0x0060, r1
  d2:	df cf       	rjmp	.-66     	; 0x92 <__vector_8+0x34>

    switch (direction)		/* Note [4] */
    {
        case UP:
            if (++pwm == TIMER1_TOP)
                direction = DOWN;
  d4:	81 e0       	ldi	r24, 0x01	; 1
  d6:	80 93 60 00 	sts	0x0060, r24
  da:	db cf       	rjmp	.-74     	; 0x92 <__vector_8+0x34>

000000dc <ioinit>:

void
ioinit (void)			/* Note [6] */
{
    /* Timer 1 is 10-bit PWM (8-bit PWM on some ATtinys). */
    TCCR1A = TIMER1_PWM_INIT;
  dc:	83 e8       	ldi	r24, 0x83	; 131
  de:	8f bd       	out	0x2f, r24	; 47
     * Start timer 1.
     *
     * NB: TCCR1A and TCCR1B could actually be the same register, so
     * take care to not clobber it.
     */
    TCCR1B |= TIMER1_CLOCKSOURCE;
  e0:	8e b5       	in	r24, 0x2e	; 46
  e2:	81 60       	ori	r24, 0x01	; 1
  e4:	8e bd       	out	0x2e, r24	; 46
#if defined(TIMER1_SETUP_HOOK)
    TIMER1_SETUP_HOOK();
#endif

    /* Set PWM value to 0. */
    OCR = 0;
  e6:	1b bc       	out	0x2b, r1	; 43
  e8:	1a bc       	out	0x2a, r1	; 42

    /* Enable OC1 as output. */
    DDROC = _BV (OC1);
  ea:	82 e0       	ldi	r24, 0x02	; 2
  ec:	87 bb       	out	0x17, r24	; 23

    /* Enable timer 1 overflow interrupt. */
    TIMSK = _BV (TOIE1);
  ee:	84 e0       	ldi	r24, 0x04	; 4
  f0:	89 bf       	out	0x39, r24	; 57
    sei ();
  f2:	78 94       	sei
}
  f4:	08 95       	ret

000000f6 <main>:

void
ioinit (void)			/* Note [6] */
{
    /* Timer 1 is 10-bit PWM (8-bit PWM on some ATtinys). */
    TCCR1A = TIMER1_PWM_INIT;
  f6:	83 e8       	ldi	r24, 0x83	; 131
  f8:	8f bd       	out	0x2f, r24	; 47
     * Start timer 1.
     *
     * NB: TCCR1A and TCCR1B could actually be the same register, so
     * take care to not clobber it.
     */
    TCCR1B |= TIMER1_CLOCKSOURCE;
  fa:	8e b5       	in	r24, 0x2e	; 46
  fc:	81 60       	ori	r24, 0x01	; 1
  fe:	8e bd       	out	0x2e, r24	; 46
#if defined(TIMER1_SETUP_HOOK)
    TIMER1_SETUP_HOOK();
#endif

    /* Set PWM value to 0. */
    OCR = 0;
 100:	1b bc       	out	0x2b, r1	; 43
 102:	1a bc       	out	0x2a, r1	; 42

    /* Enable OC1 as output. */
    DDROC = _BV (OC1);
 104:	82 e0       	ldi	r24, 0x02	; 2
 106:	87 bb       	out	0x17, r24	; 23

    /* Enable timer 1 overflow interrupt. */
    TIMSK = _BV (TOIE1);
 108:	84 e0       	ldi	r24, 0x04	; 4
 10a:	89 bf       	out	0x39, r24	; 57
    sei ();
 10c:	78 94       	sei
    ioinit ();

    /* loop forever, the interrupts are doing the rest */

    for (;;)			/* Note [7] */
        sleep_mode();
 10e:	85 b7       	in	r24, 0x35	; 53
 110:	80 68       	ori	r24, 0x80	; 128
 112:	85 bf       	out	0x35, r24	; 53
 114:	88 95       	sleep
 116:	85 b7       	in	r24, 0x35	; 53
 118:	8f 77       	andi	r24, 0x7F	; 127
 11a:	85 bf       	out	0x35, r24	; 53
 11c:	f8 cf       	rjmp	.-16     	; 0x10e <main+0x18>

0000011e <_exit>:
 11e:	f8 94       	cli

00000120 <__stop_program>:
 120:	ff cf       	rjmp	.-2      	; 0x120 <__stop_program>
