
largedemo.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000006d2  00000000  00000000  000000b4  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         00000002  00800060  000006d2  00000786  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000008  00800062  00800062  00000788  2**0
                  ALLOC
  3 .noinit       00000001  0080006a  0080006a  00000788  2**0
                  ALLOC
  4 .eeprom       00000002  00810000  00810000  00000788  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  5 .debug_aranges 00000028  00000000  00000000  0000078a  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_pubnames 000000b0  00000000  00000000  000007b2  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_info   000008ff  00000000  00000000  00000862  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_abbrev 000002c6  00000000  00000000  00001161  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_line   00000601  00000000  00000000  00001427  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_frame  00000090  00000000  00000000  00001a28  2**2
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_str    000001f7  00000000  00000000  00001ab8  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_loc    0000033b  00000000  00000000  00001caf  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 000001b8  00000000  00000000  00001fea  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 c4 00 	jmp	0x188	; 0x188 <__ctors_end>
   4:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
   8:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
   c:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  10:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  14:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  18:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  1c:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  20:	0c 94 fb 00 	jmp	0x1f6	; 0x1f6 <__vector_8>
  24:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  28:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  2c:	0c 94 30 01 	jmp	0x260	; 0x260 <__vector_11>
  30:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  34:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  38:	0c 94 16 01 	jmp	0x22c	; 0x22c <__vector_14>
  3c:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  40:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  44:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  48:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  4c:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>
  50:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__bad_interrupt>

00000054 <__c.1641>:
  54:	0a 7a 7a 7a 7a 2e 2e 2e 20 7a 7a 7a 2e 2e 2e 00     .zzzz... zzz....

00000064 <__c.1633>:
  64:	0a 57 65 6c 63 6f 6d 65 20 61 74 20 73 65 72 69     .Welcome at seri
  74:	61 6c 20 63 6f 6e 74 72 6f 6c 2c 20 74 79 70 65     al control, type
  84:	20 2b 2f 2d 20 74 6f 20 61 64 6a 75 73 74 2c 20      +/- to adjust, 
  94:	6f 72 20 30 2f 31 20 74 6f 20 74 75 72 6e 20 6f     or 0/1 to turn o
  a4:	6e 2f 6f 66 66 0a 74 68 65 20 4c 45 44 2c 20 71     n/off.the LED, q
  b4:	20 74 6f 20 71 75 69 74 20 73 65 72 69 61 6c 20      to quit serial 
  c4:	6d 6f 64 65 2c 20 72 20 74 6f 20 64 65 6d 6f 6e     mode, r to demon
  d4:	73 74 72 61 74 65 20 61 20 77 61 74 63 68 64 6f     strate a watchdo
  e4:	67 20 72 65 73 65 74 0a 00                          g reset..

000000ed <__c.1631>:
  ed:	0a 54 68 61 6e 6b 20 79 6f 75 20 66 6f 72 20 75     .Thank you for u
  fd:	73 69 6e 67 20 73 65 72 69 61 6c 20 6d 6f 64 65     sing serial mode
 10d:	2e 20 20 47 6f 6f 64 2d 62 79 65 21 0a 00           .  Good-bye!..

0000011b <__c.1629>:
 11b:	5b 45 45 50 52 4f 4d 20 75 70 64 61 74 65 64 5d     [EEPROM updated]
 12b:	20 00                                                .

0000012d <__c.1623>:
 12d:	0a 48 65 6c 6c 6f 2c 20 74 68 69 73 20 69 73 20     .Hello, this is 
 13d:	74 68 65 20 61 76 72 2d 67 63 63 2f 6c 69 62 63     the avr-gcc/libc
 14d:	20 64 65 6d 6f 20 72 75 6e 6e 69 6e 67 20 6f 6e      demo running on
 15d:	20 61 6e 20 41 54 6d 65 67 61 31 36 0a 00            an ATmega16..

0000016b <__c.1621>:
 16b:	0a 4f 6f 6f 70 73 2c 20 74 68 65 20 77 61 74 63     .Ooops, the watc
 17b:	68 64 6f 67 20 62 69 74 20 6d 65 21 00              hdog bit me!.

00000188 <__ctors_end>:
 188:	11 24       	eor	r1, r1
 18a:	1f be       	out	0x3f, r1	; 63
 18c:	cf e5       	ldi	r28, 0x5F	; 95
 18e:	d4 e0       	ldi	r29, 0x04	; 4
 190:	de bf       	out	0x3e, r29	; 62
 192:	cd bf       	out	0x3d, r28	; 61

00000194 <handle_mcucsr>:
 */
void handle_mcucsr(void)
  __attribute__((section(".init3")))
  __attribute__((naked));
void handle_mcucsr(void)
{
 194:	84 b7       	in	r24, 0x34	; 52
 196:	80 93 6a 00 	sts	0x006A, r24
  mcucsr = MCUCSR;
  MCUCSR = 0;
 19a:	14 be       	out	0x34, r1	; 52

0000019c <__do_copy_data>:
 19c:	10 e0       	ldi	r17, 0x00	; 0
 19e:	a0 e6       	ldi	r26, 0x60	; 96
 1a0:	b0 e0       	ldi	r27, 0x00	; 0
 1a2:	e2 ed       	ldi	r30, 0xD2	; 210
 1a4:	f6 e0       	ldi	r31, 0x06	; 6
 1a6:	02 c0       	rjmp	.+4      	; 0x1ac <.do_copy_data_start>

000001a8 <.do_copy_data_loop>:
 1a8:	05 90       	lpm	r0, Z+
 1aa:	0d 92       	st	X+, r0

000001ac <.do_copy_data_start>:
 1ac:	a2 36       	cpi	r26, 0x62	; 98
 1ae:	b1 07       	cpc	r27, r17
 1b0:	d9 f7       	brne	.-10     	; 0x1a8 <.do_copy_data_loop>

000001b2 <__do_clear_bss>:
 1b2:	10 e0       	ldi	r17, 0x00	; 0
 1b4:	a2 e6       	ldi	r26, 0x62	; 98
 1b6:	b0 e0       	ldi	r27, 0x00	; 0
 1b8:	01 c0       	rjmp	.+2      	; 0x1bc <.do_clear_bss_start>

000001ba <.do_clear_bss_loop>:
 1ba:	1d 92       	st	X+, r1

000001bc <.do_clear_bss_start>:
 1bc:	aa 36       	cpi	r26, 0x6A	; 106
 1be:	b1 07       	cpc	r27, r17
 1c0:	e1 f7       	brne	.-8      	; 0x1ba <.do_clear_bss_loop>
 1c2:	0e 94 9c 01 	call	0x338	; 0x338 <main>
 1c6:	0c 94 67 03 	jmp	0x6ce	; 0x6ce <_exit>

000001ca <__bad_interrupt>:
 1ca:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

000001ce <eeprom_read_byte>:

/** \ingroup avr_eeprom
    Read one byte from EEPROM address \a __p.
 */
__ATTR_PURE__ static __inline__ uint8_t eeprom_read_byte (const uint8_t *__p)
{
 1ce:	9c 01       	movw	r18, r24
    do {} while (!eeprom_is_ready ());
 1d0:	e1 99       	sbic	0x1c, 1	; 28
 1d2:	fe cf       	rjmp	.-4      	; 0x1d0 <eeprom_read_byte+0x2>
#if E2END <= 0xFF
    EEARL = (uint8_t)(uint16_t)__p;
#else
    EEAR = (uint16_t)__p;
 1d4:	3f bb       	out	0x1f, r19	; 31
 1d6:	2e bb       	out	0x1e, r18	; 30
    /* Use inline assembly below as some AVRs have problems with accessing
    EECR with STS instructions. For example, see errata for ATmega64. 
    The code below also assumes that EECR and EEDR are in the I/O space.
    */
    uint8_t __result;
    __asm__ __volatile__
 1d8:	e0 9a       	sbi	0x1c, 0	; 28
 1da:	8d b3       	in	r24, 0x1d	; 29
        : "i" (_SFR_IO_ADDR(EECR)),
          "i" (EERE),
          "i" (_SFR_IO_ADDR(EEDR))
    );
    return __result;
}
 1dc:	08 95       	ret

000001de <eeprom_write_byte>:

/** \ingroup avr_eeprom
    Write a byte \a __value to EEPROM address \a __p.
 */
static __inline__ void eeprom_write_byte (uint8_t *__p, uint8_t __value)
{
 1de:	9c 01       	movw	r18, r24
    do {} while (!eeprom_is_ready ());
 1e0:	e1 99       	sbic	0x1c, 1	; 28
 1e2:	fe cf       	rjmp	.-4      	; 0x1e0 <eeprom_write_byte+0x2>
#endif

#if	E2END <= 0xFF
    EEARL = (unsigned)__p;
#else
    EEAR = (unsigned)__p;
 1e4:	3f bb       	out	0x1f, r19	; 31
 1e6:	2e bb       	out	0x1e, r18	; 30
#endif
    EEDR = __value;
 1e8:	6d bb       	out	0x1d, r22	; 29

    __asm__ __volatile__ (
 1ea:	0f b6       	in	r0, 0x3f	; 63
 1ec:	f8 94       	cli
 1ee:	e2 9a       	sbi	0x1c, 2	; 28
 1f0:	e1 9a       	sbi	0x1c, 1	; 28
 1f2:	0f be       	out	0x3f, r0	; 63
          [__sreg]  "i" (_SFR_IO_ADDR(SREG)),
          [__eemwe] "i" (EEMWE),
          [__eewe]  "i" (EEWE)
        : "r0"
    );
}
 1f4:	08 95       	ret

000001f6 <__vector_8>:
uint8_t mcucsr __attribute__((section(".noinit")));

/* Part 3: Interrupt service routines */

ISR(TIMER1_OVF_vect)
{
 1f6:	1f 92       	push	r1
 1f8:	0f 92       	push	r0
 1fa:	0f b6       	in	r0, 0x3f	; 63
 1fc:	0f 92       	push	r0
 1fe:	11 24       	eor	r1, r1
 200:	8f 93       	push	r24
  static uint8_t scaler = TMR1_SCALE;

  if (--scaler == 0)
 202:	80 91 60 00 	lds	r24, 0x0060
 206:	81 50       	subi	r24, 0x01	; 1
 208:	80 93 60 00 	sts	0x0060, r24
 20c:	88 23       	and	r24, r24
 20e:	41 f4       	brne	.+16     	; 0x220 <__vector_8+0x2a>
    {
      scaler = TMR1_SCALE;
 210:	85 e0       	ldi	r24, 0x05	; 5
 212:	80 93 60 00 	sts	0x0060, r24
      intflags.tmr_int = 1;
 216:	80 91 69 00 	lds	r24, 0x0069
 21a:	81 60       	ori	r24, 0x01	; 1
 21c:	80 93 69 00 	sts	0x0069, r24
    }
}
 220:	8f 91       	pop	r24
 222:	0f 90       	pop	r0
 224:	0f be       	out	0x3f, r0	; 63
 226:	0f 90       	pop	r0
 228:	1f 90       	pop	r1
 22a:	18 95       	reti

0000022c <__vector_14>:
/*
 * ADC conversion complete.  Fetch the 10-bit value, and feed the
 * PWM with it.
 */
ISR(ADC_vect)
{
 22c:	1f 92       	push	r1
 22e:	0f 92       	push	r0
 230:	0f b6       	in	r0, 0x3f	; 63
 232:	0f 92       	push	r0
 234:	11 24       	eor	r1, r1
 236:	8f 93       	push	r24
 238:	9f 93       	push	r25
  adcval = ADCW;
 23a:	84 b1       	in	r24, 0x04	; 4
 23c:	95 b1       	in	r25, 0x05	; 5
 23e:	90 93 68 00 	sts	0x0068, r25
 242:	80 93 67 00 	sts	0x0067, r24
  ADCSRA &= ~_BV(ADIE);		/* disable ADC interrupt */
 246:	33 98       	cbi	0x06, 3	; 6
  intflags.adc_int = 1;
 248:	80 91 69 00 	lds	r24, 0x0069
 24c:	82 60       	ori	r24, 0x02	; 2
 24e:	80 93 69 00 	sts	0x0069, r24
}
 252:	9f 91       	pop	r25
 254:	8f 91       	pop	r24
 256:	0f 90       	pop	r0
 258:	0f be       	out	0x3f, r0	; 63
 25a:	0f 90       	pop	r0
 25c:	1f 90       	pop	r1
 25e:	18 95       	reti

00000260 <__vector_11>:
 * UART receive interrupt.  Fetch the character received and buffer
 * it, unless there was a framing error.  Note that the main loop
 * checks the received character only once per 10 ms.
 */
ISR(USART_RXC_vect)
{
 260:	1f 92       	push	r1
 262:	0f 92       	push	r0
 264:	0f b6       	in	r0, 0x3f	; 63
 266:	0f 92       	push	r0
 268:	11 24       	eor	r1, r1
 26a:	8f 93       	push	r24
  uint8_t c;

  c = UDR;
 26c:	8c b1       	in	r24, 0x0c	; 12
  if (bit_is_clear(UCSRA, FE))
 26e:	5c 99       	sbic	0x0b, 4	; 11
 270:	07 c0       	rjmp	.+14     	; 0x280 <__vector_11+0x20>
    {
      rxbuff = c;
 272:	80 93 64 00 	sts	0x0064, r24
      intflags.rx_int = 1;
 276:	80 91 69 00 	lds	r24, 0x0069
 27a:	84 60       	ori	r24, 0x04	; 4
 27c:	80 93 69 00 	sts	0x0069, r24
    }
}
 280:	8f 91       	pop	r24
 282:	0f 90       	pop	r0
 284:	0f be       	out	0x3f, r0	; 63
 286:	0f 90       	pop	r0
 288:	1f 90       	pop	r1
 28a:	18 95       	reti

0000028c <set_pwm>:
 * Update the PWM value.  If it has changed, send the new value down
 * the serial line.
 */
static void
set_pwm(int16_t new)
{
 28c:	0f 93       	push	r16
 28e:	1f 93       	push	r17
 290:	df 93       	push	r29
 292:	cf 93       	push	r28
 294:	cd b7       	in	r28, 0x3d	; 61
 296:	de b7       	in	r29, 0x3e	; 62
 298:	28 97       	sbiw	r28, 0x08	; 8
 29a:	0f b6       	in	r0, 0x3f	; 63
 29c:	f8 94       	cli
 29e:	de bf       	out	0x3e, r29	; 62
 2a0:	0f be       	out	0x3f, r0	; 63
 2a2:	cd bf       	out	0x3d, r28	; 61
 2a4:	23 e0       	ldi	r18, 0x03	; 3
 2a6:	89 3e       	cpi	r24, 0xE9	; 233
 2a8:	92 07       	cpc	r25, r18
 2aa:	14 f0       	brlt	.+4      	; 0x2b0 <set_pwm+0x24>
 2ac:	88 ee       	ldi	r24, 0xE8	; 232
 2ae:	93 e0       	ldi	r25, 0x03	; 3
 2b0:	9c 01       	movw	r18, r24
 2b2:	97 ff       	sbrs	r25, 7
 2b4:	02 c0       	rjmp	.+4      	; 0x2ba <set_pwm+0x2e>
 2b6:	20 e0       	ldi	r18, 0x00	; 0
 2b8:	30 e0       	ldi	r19, 0x00	; 0
  if (new < 0)
    new = 0;
  else if (new > 1000)
    new = 1000;

  if (new != pwm)
 2ba:	80 91 65 00 	lds	r24, 0x0065
 2be:	90 91 66 00 	lds	r25, 0x0066
 2c2:	28 17       	cp	r18, r24
 2c4:	39 07       	cpc	r19, r25
 2c6:	69 f1       	breq	.+90     	; 0x322 <set_pwm+0x96>
    {
      OCR1A = (pwm = new);
 2c8:	30 93 66 00 	sts	0x0066, r19
 2cc:	20 93 65 00 	sts	0x0065, r18
 2d0:	3b bd       	out	0x2b, r19	; 43
 2d2:	2a bd       	out	0x2a, r18	; 42
      /*
       * Calculate a "percentage".  We just divide by 10, as we
       * limited the max value of the PWM to 1000 above.
       */
      new /= 10;
      itoa(new, s, 10);
 2d4:	c9 01       	movw	r24, r18
 2d6:	6a e0       	ldi	r22, 0x0A	; 10
 2d8:	70 e0       	ldi	r23, 0x00	; 0
 2da:	0e 94 40 03 	call	0x680	; 0x680 <__divmodhi4>
 2de:	cb 01       	movw	r24, r22
 2e0:	8e 01       	movw	r16, r28
 2e2:	0f 5f       	subi	r16, 0xFF	; 255
 2e4:	1f 4f       	sbci	r17, 0xFF	; 255
 2e6:	b8 01       	movw	r22, r16
 2e8:	4a e0       	ldi	r20, 0x0A	; 10
 2ea:	50 e0       	ldi	r21, 0x00	; 0
 2ec:	0e 94 0f 03 	call	0x61e	; 0x61e <itoa>
 2f0:	f8 01       	movw	r30, r16
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 2f2:	9d e0       	ldi	r25, 0x0D	; 13
 2f4:	09 c0       	rjmp	.+18     	; 0x308 <set_pwm+0x7c>
printstr(const char *s)
{

  while (*s)
    {
      if (*s == '\n')
 2f6:	8a 30       	cpi	r24, 0x0A	; 10
 2f8:	19 f4       	brne	.+6      	; 0x300 <set_pwm+0x74>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 2fa:	5d 9b       	sbis	0x0b, 5	; 11
 2fc:	fe cf       	rjmp	.-4      	; 0x2fa <set_pwm+0x6e>
  UDR = c;
 2fe:	9c b9       	out	0x0c, r25	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 300:	5d 9b       	sbis	0x0b, 5	; 11
 302:	fe cf       	rjmp	.-4      	; 0x300 <set_pwm+0x74>

  while (*s)
    {
      if (*s == '\n')
	putchr('\r');
      putchr(*s++);
 304:	31 96       	adiw	r30, 0x01	; 1
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 306:	8c b9       	out	0x0c, r24	; 12
 */
static void
printstr(const char *s)
{

  while (*s)
 308:	80 81       	ld	r24, Z
 30a:	88 23       	and	r24, r24
 30c:	a1 f7       	brne	.-24     	; 0x2f6 <set_pwm+0x6a>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 30e:	5d 9b       	sbis	0x0b, 5	; 11
 310:	fe cf       	rjmp	.-4      	; 0x30e <set_pwm+0x82>
  UDR = c;
 312:	80 e2       	ldi	r24, 0x20	; 32
 314:	8c b9       	out	0x0c, r24	; 12
      new /= 10;
      itoa(new, s, 10);
      printstr(s);
      putchr(' ');

      pwm_backup_tmr = EE_UPDATE_TIME;
 316:	8c e2       	ldi	r24, 0x2C	; 44
 318:	91 e0       	ldi	r25, 0x01	; 1
 31a:	90 93 63 00 	sts	0x0063, r25
 31e:	80 93 62 00 	sts	0x0062, r24
    }
}
 322:	28 96       	adiw	r28, 0x08	; 8
 324:	0f b6       	in	r0, 0x3f	; 63
 326:	f8 94       	cli
 328:	de bf       	out	0x3e, r29	; 62
 32a:	0f be       	out	0x3f, r0	; 63
 32c:	cd bf       	out	0x3d, r28	; 61
 32e:	cf 91       	pop	r28
 330:	df 91       	pop	r29
 332:	1f 91       	pop	r17
 334:	0f 91       	pop	r16
 336:	08 95       	ret

00000338 <main>:

/* Part 5: main() */

int
main(void)
{
 338:	bf 92       	push	r11
 33a:	cf 92       	push	r12
 33c:	df 92       	push	r13
 33e:	ef 92       	push	r14
 340:	ff 92       	push	r15
 342:	0f 93       	push	r16
 344:	1f 93       	push	r17
   * WGM11 bits), with OC1A used as PWM output.  OC1A will be set when
   * up-counting, and cleared when down-counting (COM1A1|COM1A0), this
   * matches the behaviour needed by the STK500's low-active LEDs.
   * The timer will runn on full MCU clock (1 MHz, CS10 in TCCR1B).
   */
  TCCR1A = _BV(WGM10) | _BV(WGM11) | _BV(COM1A1) | _BV(COM1A0);
 346:	83 ec       	ldi	r24, 0xC3	; 195
 348:	8f bd       	out	0x2f, r24	; 47
  TCCR1B = _BV(CS10);
 34a:	81 e0       	ldi	r24, 0x01	; 1
 34c:	8e bd       	out	0x2e, r24	; 46

  OCR1A = 0;			/* set PWM value to 0 */
 34e:	1b bc       	out	0x2b, r1	; 43
 350:	1a bc       	out	0x2a, r1	; 42

  /* enable pull-ups for pushbuttons */
#if HAVE_ADC
  CONTROL_PORT = _BV(TRIGGER_DOWN) | _BV(TRIGGER_UP) | _BV(TRIGGER_ADC);
 352:	8c e1       	ldi	r24, 0x1C	; 28
 354:	82 bb       	out	0x12, r24	; 18
   * Enable Port D outputs: PD6 for the clock output, PD7 for the LED
   * flasher.  PD1 is UART TxD but not DDRD setting is provided for
   * that, as enabling the UART transmitter will automatically turn
   * this pin into an output.
   */
  CONTROL_DDR = _BV(CLOCKOUT) | _BV(FLASH);
 356:	80 ec       	ldi	r24, 0xC0	; 192
 358:	81 bb       	out	0x11, r24	; 17
   * As the location of OC1A differs between supported MCU types, we
   * enable that output separately here.  Note that the DDRx register
   * *might* be the same as CONTROL_DDR above, so make sure to not
   * clobber it.
   */
  PWMDDR |= _BV(PWMOUT);
 35a:	8d 9a       	sbi	0x11, 5	; 17

  UCSRA = _BV(U2X);		/* improves baud rate error @ F_CPU = 1 MHz */
 35c:	82 e0       	ldi	r24, 0x02	; 2
 35e:	8b b9       	out	0x0b, r24	; 11
  UCSRB = _BV(TXEN)|_BV(RXEN)|_BV(RXCIE); /* tx/rx enable, rx complete intr */
 360:	88 e9       	ldi	r24, 0x98	; 152
 362:	8a b9       	out	0x0a, r24	; 10
  UBRRL = (F_CPU / (8 * 9600UL)) - 1;  /* 9600 Bd */
 364:	8c e0       	ldi	r24, 0x0C	; 12
 366:	89 b9       	out	0x09, r24	; 9

#if HAVE_ADC
  /*
   * enable ADC, select ADC clock = F_CPU / 8 (i.e. 125 kHz)
   */
  ADCSRA = _BV(ADEN) | _BV(ADPS1) | _BV(ADPS0);
 368:	83 e8       	ldi	r24, 0x83	; 131
 36a:	86 b9       	out	0x06, r24	; 6
#endif

  TIMSK = _BV(TOIE1);
 36c:	84 e0       	ldi	r24, 0x04	; 4
 36e:	89 bf       	out	0x39, r24	; 57
  sei();			/* enable interrupts */
 370:	78 94       	sei

  /*
   * Enable the watchdog with the largest prescaler.  Will cause a
   * watchdog reset after approximately 2 s @ Vcc = 5 V
   */
  wdt_enable(WDTO_2S);
 372:	2f e0       	ldi	r18, 0x0F	; 15
 374:	88 e1       	ldi	r24, 0x18	; 24
 376:	90 e0       	ldi	r25, 0x00	; 0
 378:	0f b6       	in	r0, 0x3f	; 63
 37a:	f8 94       	cli
 37c:	a8 95       	wdr
 37e:	81 bd       	out	0x21, r24	; 33
 380:	0f be       	out	0x3f, r0	; 63
 382:	21 bd       	out	0x21, r18	; 33
    Read one 16-bit word (little endian) from EEPROM address \a __p.
 */
__ATTR_PURE__ static __inline__ uint16_t eeprom_read_word (const uint16_t *__p)
{
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
    return __eerd_word (__p, eeprom_read_byte);
 384:	80 e0       	ldi	r24, 0x00	; 0
 386:	90 e0       	ldi	r25, 0x00	; 0
 388:	67 ee       	ldi	r22, 0xE7	; 231
 38a:	70 e0       	ldi	r23, 0x00	; 0
 38c:	0e 94 e4 02 	call	0x5c8	; 0x5c8 <__eerd_word>

  /*
   * Read the value from EEPROM.  If it is not 0xffff (erased cells),
   * use it as the starting value for the PWM.
   */
  if ((pwm_from_eeprom = eeprom_read_word(&ee_pwm)) != 0xffff)
 390:	2f ef       	ldi	r18, 0xFF	; 255
 392:	8f 3f       	cpi	r24, 0xFF	; 255
 394:	92 07       	cpc	r25, r18
 396:	31 f0       	breq	.+12     	; 0x3a4 <main+0x6c>
    OCR1A = (pwm = pwm_from_eeprom);
 398:	90 93 66 00 	sts	0x0066, r25
 39c:	80 93 65 00 	sts	0x0065, r24
 3a0:	9b bd       	out	0x2b, r25	; 43
 3a2:	8a bd       	out	0x2a, r24	; 42
  } __attribute__((packed)) mode = MODE_UPDOWN;
  uint8_t flash = 0;

  ioinit();

  if ((mcucsr & _BV(WDRF)) == _BV(WDRF))
 3a4:	80 91 6a 00 	lds	r24, 0x006A
 3a8:	83 ff       	sbrs	r24, 3
 3aa:	11 c0       	rjmp	.+34     	; 0x3ce <main+0x96>
    printstr_p(PSTR("\nOoops, the watchdog bit me!"));
 3ac:	eb e6       	ldi	r30, 0x6B	; 107
 3ae:	f1 e0       	ldi	r31, 0x01	; 1
 3b0:	84 91       	lpm	r24, Z+
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 3b2:	9d e0       	ldi	r25, 0x0D	; 13
 3b4:	0a c0       	rjmp	.+20     	; 0x3ca <main+0x92>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 3b6:	8a 30       	cpi	r24, 0x0A	; 10
 3b8:	19 f4       	brne	.+6      	; 0x3c0 <main+0x88>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 3ba:	5d 9b       	sbis	0x0b, 5	; 11
 3bc:	fe cf       	rjmp	.-4      	; 0x3ba <main+0x82>
  UDR = c;
 3be:	9c b9       	out	0x0c, r25	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 3c0:	5d 9b       	sbis	0x0b, 5	; 11
 3c2:	fe cf       	rjmp	.-4      	; 0x3c0 <main+0x88>
  UDR = c;
 3c4:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 3c6:	31 96       	adiw	r30, 0x01	; 1
 3c8:	84 91       	lpm	r24, Z+
 3ca:	88 23       	and	r24, r24
 3cc:	a1 f7       	brne	.-24     	; 0x3b6 <main+0x7e>
  ioinit();

  if ((mcucsr & _BV(WDRF)) == _BV(WDRF))
    printstr_p(PSTR("\nOoops, the watchdog bit me!"));

  printstr_p(PSTR("\nHello, this is the avr-gcc/libc "
 3ce:	ed e2       	ldi	r30, 0x2D	; 45
 3d0:	f1 e0       	ldi	r31, 0x01	; 1
 3d2:	84 91       	lpm	r24, Z+
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 3d4:	9d e0       	ldi	r25, 0x0D	; 13
 3d6:	0a c0       	rjmp	.+20     	; 0x3ec <main+0xb4>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 3d8:	8a 30       	cpi	r24, 0x0A	; 10
 3da:	19 f4       	brne	.+6      	; 0x3e2 <main+0xaa>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 3dc:	5d 9b       	sbis	0x0b, 5	; 11
 3de:	fe cf       	rjmp	.-4      	; 0x3dc <main+0xa4>
  UDR = c;
 3e0:	9c b9       	out	0x0c, r25	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 3e2:	5d 9b       	sbis	0x0b, 5	; 11
 3e4:	fe cf       	rjmp	.-4      	; 0x3e2 <main+0xaa>
  UDR = c;
 3e6:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 3e8:	31 96       	adiw	r30, 0x01	; 1
 3ea:	84 91       	lpm	r24, Z+
 3ec:	88 23       	and	r24, r24
 3ee:	a1 f7       	brne	.-24     	; 0x3d8 <main+0xa0>
 3f0:	10 e0       	ldi	r17, 0x00	; 0
 3f2:	00 e0       	ldi	r16, 0x00	; 0
	  intflags.tmr_int = 0;
	  /*
	   * toggle PD6, just to show the internal clock; should
	   * yield ~ 48 Hz on PD6
	   */
	  CONTROL_PORT ^= _BV(CLOCKOUT);
 3f4:	90 e4       	ldi	r25, 0x40	; 64
 3f6:	b9 2e       	mov	r11, r25
	       * PWM value in EEPROM.  Note that this function might
	       * block for a few milliseconds (after writing the
	       * first byte).
	       */
	      eeprom_write_word(&ee_pwm, pwm);
	      printstr_p(PSTR("[EEPROM updated] "));
 3f8:	eb e1       	ldi	r30, 0x1B	; 27
 3fa:	f1 e0       	ldi	r31, 0x01	; 1
 3fc:	c4 90       	lpm	r12, Z+
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 3fe:	8d e0       	ldi	r24, 0x0D	; 13
 400:	f8 2e       	mov	r15, r24
	    }
	  else
	    {
	      if (mode != MODE_SERIAL)
		{
		  printstr_p(PSTR("\nWelcome at serial control, "
 402:	e4 e6       	ldi	r30, 0x64	; 100
 404:	f0 e0       	ldi	r31, 0x00	; 0
 406:	d4 90       	lpm	r13, Z+
	{
	  intflags.rx_int = 0;

	  if (rxbuff == 'q')
	    {
	      printstr_p(PSTR("\nThank you for using serial mode."
 408:	ed ee       	ldi	r30, 0xED	; 237
 40a:	f0 e0       	ldi	r31, 0x00	; 0
 40c:	e4 90       	lpm	r14, Z+
#endif
		  "\n"));

  for (;;)
    {
      wdt_reset();
 40e:	a8 95       	wdr

      if (intflags.tmr_int)
 410:	80 91 69 00 	lds	r24, 0x0069
 414:	80 ff       	sbrs	r24, 0
 416:	59 c0       	rjmp	.+178    	; 0x4ca <__stack+0x6b>
	{
	  /*
	   * Our periodic 10 ms interrupt happened.  See what we can
	   * do about it.
	   */
	  intflags.tmr_int = 0;
 418:	80 91 69 00 	lds	r24, 0x0069
 41c:	8e 7f       	andi	r24, 0xFE	; 254
 41e:	80 93 69 00 	sts	0x0069, r24
	  /*
	   * toggle PD6, just to show the internal clock; should
	   * yield ~ 48 Hz on PD6
	   */
	  CONTROL_PORT ^= _BV(CLOCKOUT);
 422:	82 b3       	in	r24, 0x12	; 18
 424:	8b 25       	eor	r24, r11
 426:	82 bb       	out	0x12, r24	; 18
	  /*
	   * flash LED on PD7, approximately once per second
	   */
	  flash++;
 428:	0f 5f       	subi	r16, 0xFF	; 255
	  if (flash == 5)
 42a:	05 30       	cpi	r16, 0x05	; 5
 42c:	11 f4       	brne	.+4      	; 0x432 <main+0xfa>
	    CONTROL_PORT |= _BV(FLASH);
 42e:	97 9a       	sbi	0x12, 7	; 18
 430:	04 c0       	rjmp	.+8      	; 0x43a <main+0x102>
	  else if (flash == 100)
 432:	04 36       	cpi	r16, 0x64	; 100
 434:	11 f4       	brne	.+4      	; 0x43a <main+0x102>
	    {
	      flash = 0;
	      CONTROL_PORT &= ~_BV(FLASH);
 436:	97 98       	cbi	0x12, 7	; 18
 438:	00 e0       	ldi	r16, 0x00	; 0
	    }

	  switch (mode)
 43a:	11 23       	and	r17, r17
 43c:	19 f0       	breq	.+6      	; 0x444 <main+0x10c>
 43e:	11 30       	cpi	r17, 0x01	; 1
 440:	e9 f4       	brne	.+58     	; 0x47c <__stack+0x1d>
 442:	16 c0       	rjmp	.+44     	; 0x470 <__stack+0x11>
	       * NB: watch out to use PINx for reading, as opposed
	       * to using PORTx which would be the mirror of the
	       * _output_ latch register (resp. pullup configuration
	       * bit for input pins)!
	       */
	      if (bit_is_clear(PIND, TRIGGER_DOWN))
 444:	82 99       	sbic	0x10, 2	; 16
 446:	06 c0       	rjmp	.+12     	; 0x454 <main+0x11c>
		set_pwm(pwm - 10);
 448:	80 91 65 00 	lds	r24, 0x0065
 44c:	90 91 66 00 	lds	r25, 0x0066
 450:	0a 97       	sbiw	r24, 0x0a	; 10
 452:	07 c0       	rjmp	.+14     	; 0x462 <__stack+0x3>
	      else if (bit_is_clear(PIND, TRIGGER_UP))
 454:	83 99       	sbic	0x10, 3	; 16
 456:	08 c0       	rjmp	.+16     	; 0x468 <__stack+0x9>
		set_pwm(pwm + 10);
 458:	80 91 65 00 	lds	r24, 0x0065
 45c:	90 91 66 00 	lds	r25, 0x0066
 460:	0a 96       	adiw	r24, 0x0a	; 10
 462:	0e 94 46 01 	call	0x28c	; 0x28c <set_pwm>
 466:	0a c0       	rjmp	.+20     	; 0x47c <__stack+0x1d>
#if HAVE_ADC
	      else if (bit_is_clear(PIND, TRIGGER_ADC))
 468:	84 99       	sbic	0x10, 4	; 16
 46a:	08 c0       	rjmp	.+16     	; 0x47c <__stack+0x1d>
 46c:	11 e0       	ldi	r17, 0x01	; 1
 46e:	06 c0       	rjmp	.+12     	; 0x47c <__stack+0x1d>
#endif
	      break;

	    case MODE_ADC:
#if HAVE_ADC
	      if (bit_is_set(PIND, TRIGGER_ADC))
 470:	84 9b       	sbis	0x10, 4	; 16
 472:	02 c0       	rjmp	.+4      	; 0x478 <__stack+0x19>
 474:	10 e0       	ldi	r17, 0x00	; 0
 476:	02 c0       	rjmp	.+4      	; 0x47c <__stack+0x1d>
	      else
		{
		  /*
		   * Start one conversion.
		   */
		  ADCSRA |= _BV(ADIE);
 478:	33 9a       	sbi	0x06, 3	; 6
		  ADCSRA |= _BV(ADSC);
 47a:	36 9a       	sbi	0x06, 6	; 6
		}
#endif /* HAVE_ADC */
	      break;
	    }

	  if (pwm_backup_tmr && --pwm_backup_tmr == 0)
 47c:	80 91 62 00 	lds	r24, 0x0062
 480:	90 91 63 00 	lds	r25, 0x0063
 484:	00 97       	sbiw	r24, 0x00	; 0
 486:	09 f1       	breq	.+66     	; 0x4ca <__stack+0x6b>
 488:	01 97       	sbiw	r24, 0x01	; 1
 48a:	90 93 63 00 	sts	0x0063, r25
 48e:	80 93 62 00 	sts	0x0062, r24
 492:	89 2b       	or	r24, r25
 494:	d1 f4       	brne	.+52     	; 0x4ca <__stack+0x6b>
    Write a word \a __value to EEPROM address \a __p.
 */
static __inline__ void eeprom_write_word (uint16_t *__p, uint16_t __value)
{
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
    __eewr_word (__p, __value, eeprom_write_byte);
 496:	60 91 65 00 	lds	r22, 0x0065
 49a:	70 91 66 00 	lds	r23, 0x0066
 49e:	80 e0       	ldi	r24, 0x00	; 0
 4a0:	90 e0       	ldi	r25, 0x00	; 0
 4a2:	4f ee       	ldi	r20, 0xEF	; 239
 4a4:	50 e0       	ldi	r21, 0x00	; 0
 4a6:	0e 94 fa 02 	call	0x5f4	; 0x5f4 <__eewr_word>
	       * PWM value in EEPROM.  Note that this function might
	       * block for a few milliseconds (after writing the
	       * first byte).
	       */
	      eeprom_write_word(&ee_pwm, pwm);
	      printstr_p(PSTR("[EEPROM updated] "));
 4aa:	8c 2d       	mov	r24, r12
 4ac:	eb e1       	ldi	r30, 0x1B	; 27
 4ae:	f1 e0       	ldi	r31, 0x01	; 1
 4b0:	0a c0       	rjmp	.+20     	; 0x4c6 <__stack+0x67>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 4b2:	8a 30       	cpi	r24, 0x0A	; 10
 4b4:	19 f4       	brne	.+6      	; 0x4bc <__stack+0x5d>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 4b6:	5d 9b       	sbis	0x0b, 5	; 11
 4b8:	fe cf       	rjmp	.-4      	; 0x4b6 <__stack+0x57>
  UDR = c;
 4ba:	fc b8       	out	0x0c, r15	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 4bc:	5d 9b       	sbis	0x0b, 5	; 11
 4be:	fe cf       	rjmp	.-4      	; 0x4bc <__stack+0x5d>
  UDR = c;
 4c0:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 4c2:	31 96       	adiw	r30, 0x01	; 1
 4c4:	84 91       	lpm	r24, Z+
 4c6:	88 23       	and	r24, r24
 4c8:	a1 f7       	brne	.-24     	; 0x4b2 <__stack+0x53>
	      printstr_p(PSTR("[EEPROM updated] "));
	    }
	}

#if HAVE_ADC
      if (intflags.adc_int)
 4ca:	80 91 69 00 	lds	r24, 0x0069
 4ce:	81 ff       	sbrs	r24, 1
 4d0:	0b c0       	rjmp	.+22     	; 0x4e8 <__stack+0x89>
	{
	  intflags.adc_int = 0;
 4d2:	80 91 69 00 	lds	r24, 0x0069
 4d6:	8d 7f       	andi	r24, 0xFD	; 253
 4d8:	80 93 69 00 	sts	0x0069, r24
	  set_pwm(adcval);
 4dc:	80 91 67 00 	lds	r24, 0x0067
 4e0:	90 91 68 00 	lds	r25, 0x0068
 4e4:	0e 94 46 01 	call	0x28c	; 0x28c <set_pwm>
	}
#endif /* HAVE_ADC */

      if (intflags.rx_int)
 4e8:	80 91 69 00 	lds	r24, 0x0069
 4ec:	82 ff       	sbrs	r24, 2
 4ee:	64 c0       	rjmp	.+200    	; 0x5b8 <__stack+0x159>
	{
	  intflags.rx_int = 0;
 4f0:	80 91 69 00 	lds	r24, 0x0069
 4f4:	8b 7f       	andi	r24, 0xFB	; 251
 4f6:	80 93 69 00 	sts	0x0069, r24

	  if (rxbuff == 'q')
 4fa:	80 91 64 00 	lds	r24, 0x0064
 4fe:	81 37       	cpi	r24, 0x71	; 113
 500:	89 f4       	brne	.+34     	; 0x524 <__stack+0xc5>
	    {
	      printstr_p(PSTR("\nThank you for using serial mode."
 502:	8e 2d       	mov	r24, r14
 504:	ed ee       	ldi	r30, 0xED	; 237
 506:	f0 e0       	ldi	r31, 0x00	; 0
 508:	0a c0       	rjmp	.+20     	; 0x51e <__stack+0xbf>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 50a:	8a 30       	cpi	r24, 0x0A	; 10
 50c:	19 f4       	brne	.+6      	; 0x514 <__stack+0xb5>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 50e:	5d 9b       	sbis	0x0b, 5	; 11
 510:	fe cf       	rjmp	.-4      	; 0x50e <__stack+0xaf>
  UDR = c;
 512:	fc b8       	out	0x0c, r15	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 514:	5d 9b       	sbis	0x0b, 5	; 11
 516:	fe cf       	rjmp	.-4      	; 0x514 <__stack+0xb5>
  UDR = c;
 518:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 51a:	31 96       	adiw	r30, 0x01	; 1
 51c:	84 91       	lpm	r24, Z+
 51e:	88 23       	and	r24, r24
 520:	a1 f7       	brne	.-24     	; 0x50a <__stack+0xab>
 522:	49 c0       	rjmp	.+146    	; 0x5b6 <__stack+0x157>
			      "  Good-bye!\n"));
	      mode = MODE_UPDOWN;
	    }
	  else
	    {
	      if (mode != MODE_SERIAL)
 524:	12 30       	cpi	r17, 0x02	; 2
 526:	89 f0       	breq	.+34     	; 0x54a <__stack+0xeb>
		{
		  printstr_p(PSTR("\nWelcome at serial control, "
 528:	8d 2d       	mov	r24, r13
 52a:	e4 e6       	ldi	r30, 0x64	; 100
 52c:	f0 e0       	ldi	r31, 0x00	; 0
 52e:	0a c0       	rjmp	.+20     	; 0x544 <__stack+0xe5>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 530:	8a 30       	cpi	r24, 0x0A	; 10
 532:	19 f4       	brne	.+6      	; 0x53a <__stack+0xdb>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 534:	5d 9b       	sbis	0x0b, 5	; 11
 536:	fe cf       	rjmp	.-4      	; 0x534 <__stack+0xd5>
  UDR = c;
 538:	fc b8       	out	0x0c, r15	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 53a:	5d 9b       	sbis	0x0b, 5	; 11
 53c:	fe cf       	rjmp	.-4      	; 0x53a <__stack+0xdb>
  UDR = c;
 53e:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 540:	31 96       	adiw	r30, 0x01	; 1
 542:	84 91       	lpm	r24, Z+
 544:	88 23       	and	r24, r24
 546:	a1 f7       	brne	.-24     	; 0x530 <__stack+0xd1>
 548:	12 e0       	ldi	r17, 0x02	; 2
				  "type +/- to adjust, or 0/1 to turn on/off\n"
				  "the LED, q to quit serial mode, "
				  "r to demonstrate a watchdog reset\n"));
		  mode = MODE_SERIAL;
		}
	      switch (rxbuff)
 54a:	80 91 64 00 	lds	r24, 0x0064
 54e:	80 33       	cpi	r24, 0x30	; 48
 550:	d1 f0       	breq	.+52     	; 0x586 <__stack+0x127>
 552:	81 33       	cpi	r24, 0x31	; 49
 554:	2c f4       	brge	.+10     	; 0x560 <__stack+0x101>
 556:	8b 32       	cpi	r24, 0x2B	; 43
 558:	41 f0       	breq	.+16     	; 0x56a <__stack+0x10b>
 55a:	8d 32       	cpi	r24, 0x2D	; 45
 55c:	69 f5       	brne	.+90     	; 0x5b8 <__stack+0x159>
 55e:	0b c0       	rjmp	.+22     	; 0x576 <__stack+0x117>
 560:	81 33       	cpi	r24, 0x31	; 49
 562:	a1 f0       	breq	.+40     	; 0x58c <__stack+0x12d>
 564:	82 37       	cpi	r24, 0x72	; 114
 566:	41 f5       	brne	.+80     	; 0x5b8 <__stack+0x159>
 568:	14 c0       	rjmp	.+40     	; 0x592 <__stack+0x133>
		{
		case '+':
		  set_pwm(pwm + 10);
 56a:	80 91 65 00 	lds	r24, 0x0065
 56e:	90 91 66 00 	lds	r25, 0x0066
 572:	0a 96       	adiw	r24, 0x0a	; 10
 574:	05 c0       	rjmp	.+10     	; 0x580 <__stack+0x121>
		  break;

		case '-':
		  set_pwm(pwm - 10);
 576:	80 91 65 00 	lds	r24, 0x0065
 57a:	90 91 66 00 	lds	r25, 0x0066
 57e:	0a 97       	sbiw	r24, 0x0a	; 10
 580:	0e 94 46 01 	call	0x28c	; 0x28c <set_pwm>
 584:	19 c0       	rjmp	.+50     	; 0x5b8 <__stack+0x159>
		  break;

		case '0':
		  set_pwm(0);
 586:	80 e0       	ldi	r24, 0x00	; 0
 588:	90 e0       	ldi	r25, 0x00	; 0
 58a:	fa cf       	rjmp	.-12     	; 0x580 <__stack+0x121>
		  break;

		case '1':
		  set_pwm(1000);
 58c:	88 ee       	ldi	r24, 0xE8	; 232
 58e:	93 e0       	ldi	r25, 0x03	; 3
 590:	f7 cf       	rjmp	.-18     	; 0x580 <__stack+0x121>
		  break;

		case 'r':
		  printstr_p(PSTR("\nzzzz... zzz..."));
 592:	e4 e5       	ldi	r30, 0x54	; 84
 594:	f0 e0       	ldi	r31, 0x00	; 0
 596:	84 91       	lpm	r24, Z+
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
  UDR = c;
 598:	9d e0       	ldi	r25, 0x0D	; 13
 59a:	0a c0       	rjmp	.+20     	; 0x5b0 <__stack+0x151>
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
    {
      if (c == '\n')
 59c:	8a 30       	cpi	r24, 0x0A	; 10
 59e:	19 f4       	brne	.+6      	; 0x5a6 <__stack+0x147>
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 5a0:	5d 9b       	sbis	0x0b, 5	; 11
 5a2:	fe cf       	rjmp	.-4      	; 0x5a0 <__stack+0x141>
  UDR = c;
 5a4:	9c b9       	out	0x0c, r25	; 12
 */
static void
putchr(char c)
{

  loop_until_bit_is_set(UCSRA, UDRE);
 5a6:	5d 9b       	sbis	0x0b, 5	; 11
 5a8:	fe cf       	rjmp	.-4      	; 0x5a6 <__stack+0x147>
  UDR = c;
 5aa:	8c b9       	out	0x0c, r24	; 12
static void
printstr_p(const char *s)
{
  char c;

  for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s))
 5ac:	31 96       	adiw	r30, 0x01	; 1
 5ae:	84 91       	lpm	r24, Z+
 5b0:	88 23       	and	r24, r24
 5b2:	a1 f7       	brne	.-24     	; 0x59c <__stack+0x13d>
 5b4:	ff cf       	rjmp	.-2      	; 0x5b4 <__stack+0x155>
 5b6:	10 e0       	ldi	r17, 0x00	; 0
		  for (;;)
		    ;
		}
	    }
	}
      sleep_mode();
 5b8:	85 b7       	in	r24, 0x35	; 53
 5ba:	80 64       	ori	r24, 0x40	; 64
 5bc:	85 bf       	out	0x35, r24	; 53
 5be:	88 95       	sleep
 5c0:	85 b7       	in	r24, 0x35	; 53
 5c2:	8f 7b       	andi	r24, 0xBF	; 191
 5c4:	85 bf       	out	0x35, r24	; 53
 5c6:	23 cf       	rjmp	.-442    	; 0x40e <main+0xd6>

000005c8 <__eerd_word>:
 5c8:	df 92       	push	r13
 5ca:	ef 92       	push	r14
 5cc:	ff 92       	push	r15
 5ce:	0f 93       	push	r16
 5d0:	1f 93       	push	r17
 5d2:	7b 01       	movw	r14, r22
 5d4:	8c 01       	movw	r16, r24
 5d6:	fb 01       	movw	r30, r22
 5d8:	09 95       	icall
 5da:	d8 2e       	mov	r13, r24
 5dc:	c8 01       	movw	r24, r16
 5de:	01 96       	adiw	r24, 0x01	; 1
 5e0:	f7 01       	movw	r30, r14
 5e2:	09 95       	icall
 5e4:	98 2f       	mov	r25, r24
 5e6:	8d 2d       	mov	r24, r13
 5e8:	1f 91       	pop	r17
 5ea:	0f 91       	pop	r16
 5ec:	ff 90       	pop	r15
 5ee:	ef 90       	pop	r14
 5f0:	df 90       	pop	r13
 5f2:	08 95       	ret

000005f4 <__eewr_word>:
 5f4:	df 92       	push	r13
 5f6:	ef 92       	push	r14
 5f8:	ff 92       	push	r15
 5fa:	0f 93       	push	r16
 5fc:	1f 93       	push	r17
 5fe:	d7 2e       	mov	r13, r23
 600:	7a 01       	movw	r14, r20
 602:	8c 01       	movw	r16, r24
 604:	fa 01       	movw	r30, r20
 606:	09 95       	icall
 608:	c8 01       	movw	r24, r16
 60a:	01 96       	adiw	r24, 0x01	; 1
 60c:	6d 2d       	mov	r22, r13
 60e:	f7 01       	movw	r30, r14
 610:	09 95       	icall
 612:	1f 91       	pop	r17
 614:	0f 91       	pop	r16
 616:	ff 90       	pop	r15
 618:	ef 90       	pop	r14
 61a:	df 90       	pop	r13
 61c:	08 95       	ret

0000061e <itoa>:
 61e:	fb 01       	movw	r30, r22
 620:	9f 01       	movw	r18, r30
 622:	e8 94       	clt
 624:	42 30       	cpi	r20, 0x02	; 2
 626:	c4 f0       	brlt	.+48     	; 0x658 <itoa+0x3a>
 628:	45 32       	cpi	r20, 0x25	; 37
 62a:	b4 f4       	brge	.+44     	; 0x658 <itoa+0x3a>
 62c:	4a 30       	cpi	r20, 0x0A	; 10
 62e:	29 f4       	brne	.+10     	; 0x63a <itoa+0x1c>
 630:	97 fb       	bst	r25, 7
 632:	1e f4       	brtc	.+6      	; 0x63a <itoa+0x1c>
 634:	90 95       	com	r25
 636:	81 95       	neg	r24
 638:	9f 4f       	sbci	r25, 0xFF	; 255
 63a:	64 2f       	mov	r22, r20
 63c:	77 27       	eor	r23, r23
 63e:	0e 94 53 03 	call	0x6a6	; 0x6a6 <__udivmodhi4>
 642:	80 5d       	subi	r24, 0xD0	; 208
 644:	8a 33       	cpi	r24, 0x3A	; 58
 646:	0c f0       	brlt	.+2      	; 0x64a <itoa+0x2c>
 648:	89 5d       	subi	r24, 0xD9	; 217
 64a:	81 93       	st	Z+, r24
 64c:	cb 01       	movw	r24, r22
 64e:	00 97       	sbiw	r24, 0x00	; 0
 650:	a1 f7       	brne	.-24     	; 0x63a <itoa+0x1c>
 652:	16 f4       	brtc	.+4      	; 0x658 <itoa+0x3a>
 654:	5d e2       	ldi	r21, 0x2D	; 45
 656:	51 93       	st	Z+, r21
 658:	10 82       	st	Z, r1
 65a:	c9 01       	movw	r24, r18
 65c:	0c 94 30 03 	jmp	0x660	; 0x660 <strrev>

00000660 <strrev>:
 660:	dc 01       	movw	r26, r24
 662:	fc 01       	movw	r30, r24
 664:	67 2f       	mov	r22, r23
 666:	71 91       	ld	r23, Z+
 668:	77 23       	and	r23, r23
 66a:	e1 f7       	brne	.-8      	; 0x664 <strrev+0x4>
 66c:	32 97       	sbiw	r30, 0x02	; 2
 66e:	04 c0       	rjmp	.+8      	; 0x678 <strrev+0x18>
 670:	7c 91       	ld	r23, X
 672:	6d 93       	st	X+, r22
 674:	70 83       	st	Z, r23
 676:	62 91       	ld	r22, -Z
 678:	ae 17       	cp	r26, r30
 67a:	bf 07       	cpc	r27, r31
 67c:	c8 f3       	brcs	.-14     	; 0x670 <strrev+0x10>
 67e:	08 95       	ret

00000680 <__divmodhi4>:
 680:	97 fb       	bst	r25, 7
 682:	09 2e       	mov	r0, r25
 684:	07 26       	eor	r0, r23
 686:	0a d0       	rcall	.+20     	; 0x69c <__divmodhi4_neg1>
 688:	77 fd       	sbrc	r23, 7
 68a:	04 d0       	rcall	.+8      	; 0x694 <__divmodhi4_neg2>
 68c:	0c d0       	rcall	.+24     	; 0x6a6 <__udivmodhi4>
 68e:	06 d0       	rcall	.+12     	; 0x69c <__divmodhi4_neg1>
 690:	00 20       	and	r0, r0
 692:	1a f4       	brpl	.+6      	; 0x69a <__divmodhi4_exit>

00000694 <__divmodhi4_neg2>:
 694:	70 95       	com	r23
 696:	61 95       	neg	r22
 698:	7f 4f       	sbci	r23, 0xFF	; 255

0000069a <__divmodhi4_exit>:
 69a:	08 95       	ret

0000069c <__divmodhi4_neg1>:
 69c:	f6 f7       	brtc	.-4      	; 0x69a <__divmodhi4_exit>
 69e:	90 95       	com	r25
 6a0:	81 95       	neg	r24
 6a2:	9f 4f       	sbci	r25, 0xFF	; 255
 6a4:	08 95       	ret

000006a6 <__udivmodhi4>:
 6a6:	aa 1b       	sub	r26, r26
 6a8:	bb 1b       	sub	r27, r27
 6aa:	51 e1       	ldi	r21, 0x11	; 17
 6ac:	07 c0       	rjmp	.+14     	; 0x6bc <__udivmodhi4_ep>

000006ae <__udivmodhi4_loop>:
 6ae:	aa 1f       	adc	r26, r26
 6b0:	bb 1f       	adc	r27, r27
 6b2:	a6 17       	cp	r26, r22
 6b4:	b7 07       	cpc	r27, r23
 6b6:	10 f0       	brcs	.+4      	; 0x6bc <__udivmodhi4_ep>
 6b8:	a6 1b       	sub	r26, r22
 6ba:	b7 0b       	sbc	r27, r23

000006bc <__udivmodhi4_ep>:
 6bc:	88 1f       	adc	r24, r24
 6be:	99 1f       	adc	r25, r25
 6c0:	5a 95       	dec	r21
 6c2:	a9 f7       	brne	.-22     	; 0x6ae <__udivmodhi4_loop>
 6c4:	80 95       	com	r24
 6c6:	90 95       	com	r25
 6c8:	bc 01       	movw	r22, r24
 6ca:	cd 01       	movw	r24, r26
 6cc:	08 95       	ret

000006ce <_exit>:
 6ce:	f8 94       	cli

000006d0 <__stop_program>:
 6d0:	ff cf       	rjmp	.-2      	; 0x6d0 <__stop_program>
