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            <![CDATA[access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif 
end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map 
new next null of on open others out package port postponed procedure process pure range record register reject report return select severity 
shared signal subtype then to transport type unaffected units until use variable wait when while with]]>
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            <![CDATA[abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor]]>
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            <![CDATA[left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction 
event active last_event last_active last_value driving driving_value simple_name path_name instance_name]]>
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            <![CDATA[now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left 
rotate_right resize to_integer to_unsigned to_signed std_match to_01]]>
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std_logic_vector X01 X01Z UX01 UX01Z unsigned signed]]>
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