# Specify platform memories
                                                 
memory       EMMC                                driver Targets\Flash-Drivers\emmc_drv.bin parameters sid 0 width 4 delay 9 rpapi_base 0x00030400
memory       SDRAM                               parameters address 0x80000000
                                                 
# Get device definitions
                                                 
use          .\targets\definitions\definitions_omap4.txt 
                                                 
RPAPI_BASE   0x00030400                          
                                                 
MODE_32                                          
                                                 
WRITE        CM_MEMIF_EMIF_1_CLKCTRL             0x00000001
WRITE        CM_MEMIF_EMIF_2_CLKCTRL             0x00000001
POLL_VALUE   CM_MEMIF_CLKSTCTRL                  0x00000700                  0x00000700
                                                 
# DDR Init
WRITE        CONTROL_LPDDR2IO1_0                 0x9C9C9C9C
WRITE        CONTROL_LPDDR2IO1_1                 0x9C9C9C9C
WRITE        CONTROL_LPDDR2IO1_2                 0x9C9C9C9C
WRITE        CONTROL_LPDDR2IO2_0                 0x9C9C9C9C
WRITE        CONTROL_LPDDR2IO2_1                 0x9C9C9C9C
WRITE        CONTROL_LPDDR2IO2_2                 0x9C9C9C9C
WRITE        CONTROL_EFUSE_2                     0x00084000
                                                 
WRITE        DMM_LISA_MAP_REGISTER_0             LISA_MAP0_1GBYTE_INTL128
WRITE        DMM_LISA_MAP_REGISTER_1             0x00000000
WRITE        DMM_LISA_MAP_REGISTER_2             0x00000000
WRITE        DMM_LISA_MAP_REGISTER_3             0xFF020100
                                                 
COPY         DMM_LISA_MAP_REGISTER_0             MA_LISA_MAP_REGISTER_0
COPY         DMM_LISA_MAP_REGISTER_1             MA_LISA_MAP_REGISTER_1
COPY         DMM_LISA_MAP_REGISTER_2             MA_LISA_MAP_REGISTER_2
COPY         DMM_LISA_MAP_REGISTER_3             MA_LISA_MAP_REGISTER_3
                                                 
# OPP50 MEMORY
                                                 
# Removing NVM mode on nCS1 in order to select if needed 2 CS of DDRAM for each EMIF4D instance
MODIFY       EMIF2_LPDDR2_NVM_CONFIG             0xB0000000                  0x00000000  
MODIFY       EMIF1_LPDDR2_NVM_CONFIG             0xB0000000                  0x00000000  
                                                 
# Using address mapping with CS line at high order address bit
MODIFY       EMIF1_LPDDR2_NVM_CONFIG             0x08000000                  0x08000000
MODIFY       EMIF2_LPDDR2_NVM_CONFIG             0x08000000                  0x08000000
                                                 
# SDRAM CONFIG
WRITE        EMIF1_SDRAM_CONFIG                  SDRAM_CONFIG_2X_2GBIT_MAP3_CL3
                                                 
# DDR PHY CTRL 1
WRITE        EMIF1_DDR_PHY_CTRL_1                DDR_PHY_CTRL1_OPPBOOT_RL3
                                                 
# set MR0 (line CS0) register and poll 
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x00000000
POLL_ZERO    EMIF1_LPDDR2_MODE_REG_DATA          0x00000001
                                                 
# set MR0 (line CS1) register and poll 
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x80000000
POLL_ZERO    EMIF1_LPDDR2_MODE_REG_DATA          0x00000001
                                                 
# set MR10 (line CS0) register
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x0000000A
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x000000FF
                                                 
# set MR10 (line CS1) register
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x8000000A
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x000000FF
                                                 
# set MR1 (line CS0) register
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x00000001
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x00000023
                                                 
# set MR1 (line CS1) register
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x80000001
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x00000023
                                                 
# DDR PHY CTRL 2
WRITE        EMIF1_DDR_PHY_CTRL_2                0x00000000
                                                 
# READ IDLE CTRL
WRITE        EMIF1_READ_IDLE_CTRL                0x000501FF
                                                 
# PWR MGMT CTRL
WRITE        EMIF1_PWR_MGMT_CTRL                 0x80000000
                                                 
# ZQ INIT
WRITE        EMIF1_ZQ_CONFIG                     0x500B3215
                                                 
# SDRAM REF CTRL
WRITE        EMIF1_SDRAM_REF_CTRL                REF_CTRL_3_9_US_OPPBOOT
                                                 
# program shadow registers
# DDR PHY CTRL1 SHDW
WRITE        EMIF1_DDR_PHY_CTRL_1_SHDW           DDR_PHY_CTRL1_OPP50_RL6
                                                 
# READ IDLE CTRL SHDW
WRITE        EMIF1_READ_IDLE_CTRL_SHDW           0x000501FF
                                                 
# SDRAM TIM 1 SHDW
WRITE        EMIF1_SDRAM_TIM_1_SHDW              JEDEC_TIM1_OPP50
                                                 
# SDRAM TIM 2 SHDW
WRITE        EMIF1_SDRAM_TIM_2_SHDW              JEDEC_TIM2_OPP50
                                                 
# SDRAM TIM 3 SHDW
WRITE        EMIF1_SDRAM_TIM_3_SHDW              0x0048A19F
                                                 
# PWR MGMT CTRL SHDW
WRITE        EMIF1_PWR_MGMT_CTRL_SHDW            0x00000000
                                                 
# SDRAM REF CTRL SHDW
WRITE        EMIF1_SDRAM_REF_CTRL_SHDW           REF_CTRL_3_9_US_OPP50
                                                 
# set MR16 (line CS0) 
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0x40000010
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x00000000
                                                 
# set MR16 (line CS1) 
WRITE        EMIF1_LPDDR2_MODE_REG_CFG           0xC0000010
WRITE        EMIF1_LPDDR2_MODE_REG_DATA          0x00000000
                                                 
WRITE        EMIF2_SDRAM_CONFIG                  SDRAM_CONFIG_2X_2GBIT_MAP3_CL3
                                                 
# DDR PHY CTRL 1
WRITE        EMIF2_DDR_PHY_CTRL_1                DDR_PHY_CTRL1_OPPBOOT_RL3
                                                 
# set MR0 (line CS0) register and poll 
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x00000000
POLL_ZERO    EMIF2_LPDDR2_MODE_REG_DATA          0x00000001
                                                 
# set MR0 (line CS1) register and poll 
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x80000000
POLL_ZERO    EMIF2_LPDDR2_MODE_REG_DATA          0x00000001
                                                 
# set MR10 (line CS0) register
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x0000000A
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x000000FF
                                                 
# set MR10 (line CS1) register
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x8000000A
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x000000FF
                                                 
# set MR1 (line CS0) register
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x00000001
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x00000023
                                                 
# set MR1 (line CS1) register
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x80000001
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x00000023
                                                 
# DDR PHY CTRL 2
WRITE        EMIF2_DDR_PHY_CTRL_2                0x00000000
                                                 
# READ IDLE CTRL
WRITE        EMIF2_READ_IDLE_CTRL                0x000501FF
                                                 
# PWR MGMT CTRL
WRITE        EMIF2_PWR_MGMT_CTRL                 0x80000000
                                                 
# ZQ INIT
WRITE        EMIF2_ZQ_CONFIG                     0x500B3215
                                                 
# SDRAM REF CTRL
WRITE        EMIF2_SDRAM_REF_CTRL                REF_CTRL_3_9_US_OPPBOOT
                                                 
# program shadow registers
# DDR PHY CTRL1 SHDW
WRITE        EMIF2_DDR_PHY_CTRL_1_SHDW           DDR_PHY_CTRL1_OPP50_RL6
                                                 
# READ IDLE CTRL SHDW
WRITE        EMIF2_READ_IDLE_CTRL_SHDW           0x000501FF
                                                 
# SDRAM TIM 1 SHDW
WRITE        EMIF2_SDRAM_TIM_1_SHDW              JEDEC_TIM1_OPP50
                                                 
# SDRAM TIM 2 SHDW
WRITE        EMIF2_SDRAM_TIM_2_SHDW              JEDEC_TIM2_OPP50
                                                 
# SDRAM TIM 3 SHDW
WRITE        EMIF2_SDRAM_TIM_3_SHDW              0x0048A19F
                                                 
# PWR MGMT CTRL SHDW
WRITE        EMIF2_PWR_MGMT_CTRL_SHDW            0x00000000
                                                 
# SDRAM REF CTRL SHDW
WRITE        EMIF2_SDRAM_REF_CTRL_SHDW           REF_CTRL_3_9_US_OPP50
                                                 
# set MR16 (line CS0) 
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0x40000010
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x00000000
                                                 
# set MR16 (line CS1) 
WRITE        EMIF2_LPDDR2_MODE_REG_CFG           0xC0000010
WRITE        EMIF2_LPDDR2_MODE_REG_DATA          0x00000000
                                                 
                                                 
# NEW OPP50 PRCM AND CORE
                                                 
WRITE        CM_CLKMODE_DPLL_MPU                 0x00000004
POLL_ZERO    CM_IDLEST_DPLL_MPU                  0x00000001
WRITE        CM_AUTOIDLE_DPLL_MPU                0x00000000
WRITE        CM_CLKSEL_DPLL_MPU                  0x00004903
WRITE        CM_DIV_M2_DPLL_MPU                  0x00000002
WRITE        CM_CLKMODE_DPLL_MPU                 0x00000007
POLL_NZERO   CM_IDLEST_DPLL_MPU                  0x00000001
                                                 
WRITE        CM_SYS_CLKSEL                       0x00000007
WRITE        CM_CLKSEL_CORE                      0x00000110
WRITE        CM_CLKMODE_DPLL_CORE                0x00000004
POLL_ZERO    CM_IDLEST_DPLL_CORE                 0x00000001
WRITE        CM_AUTOIDLE_DPLL_CORE               0x00000000
WRITE        CM_CLKSEL_DPLL_CORE                 0x00000017
WRITE        CM_DIV_M2_DPLL_CORE                 0x00000002
WRITE        CM_DIV_M3_DPLL_CORE                 0x00000008
WRITE        CM_DIV_M4_DPLL_CORE                 0x00000008
WRITE        CM_DIV_M5_DPLL_CORE                 0x00000008
WRITE        CM_DIV_M6_DPLL_CORE                 0x00000008
WRITE        CM_DIV_M7_DPLL_CORE                 0x00000010
                                                 
MODIFY       CM_CLKSEL_DPLL_CORE                 0x0001F400 0x0001F400
WRITE        CM_MEMIF_CLKSTCTRL                  0x00000002
POLL_ZERO    CM_MEMIF_EMIF_1_CLKCTRL             0x00030000
POLL_ZERO    CM_MEMIF_EMIF_2_CLKCTRL             0x00030000
                                                 
WRITE        CM_SHADOW_FREQ_CONFIG2              0x00000045
WRITE        CM_SHADOW_FREQ_CONFIG1              0x00001709
POLL_ZERO    CM_SHADOW_FREQ_CONFIG1              0x00000001
WRITE        CM_MEMIF_CLKSTCTRL                  0x00000003
                                                 
WRITE        CM_SHADOW_FREQ_CONFIG2              0x00000044
WAIT_N       0x00002710                          
                                                 
POLL_NZERO   CM_IDLEST_DPLL_CORE                 0x00000001
                                                 
WRITE        CM_CLKMODE_DPLL_PER                 0x00000004
POLL_ZERO    CM_IDLEST_DPLL_PER                  0x00000001
                                                 
WRITE        CM_AUTOIDLE_DPLL_PER                0x00000000
#WRITE CM_CLKSEL_DPLL_PER 0x0000001F
WRITE        CM_CLKSEL_DPLL_PER                  0x00000200
WRITE        CM_DIV_M2_DPLL_PER                  0x00000008
WRITE        CM_DIV_M3_DPLL_PER                  0x0000000A
WRITE        CM_DIV_M4_DPLL_PER                  0x0000000C
WRITE        CM_DIV_M5_DPLL_PER                  0x00000009
WRITE        CM_DIV_M6_DPLL_PER                  0x00000012
WRITE        CM_DIV_M7_DPLL_PER                  0x0000000A
WRITE        CM_CLKMODE_DPLL_PER                 0x00000007
POLL_NZERO   CM_IDLEST_DPLL_PER                  0x00000001
                                                 
WRITE        EMIF1_PWR_MGMT_CTRL                 0x80000000
WRITE        EMIF2_PWR_MGMT_CTRL                 0x80000000
WRITE        EMIF1_L3_CONFIG                     0x0A0000FF
WRITE        EMIF2_L3_CONFIG                     0x0A0000FF
                                                 
# Reset EMIF PHY
MODIFY       0x4C000060                          0x00000400 0x00000400
MODIFY       0x4D000060                          0x00000400 0x00000400
WRITE        0x80000000                          0x00000000
                                                 
WRITE        PRM_VC_CFG_I2C_MODE                 0x00000000
WRITE        PRM_VC_CFG_I2C_CLK                  0x00006026
WRITE        PRM_VC_VAL_BYPASS                   0x003B5512
MODIFY       PRM_VC_VAL_BYPASS                   0x01000000 0x01000000
POLL_ZERO    PRM_VC_VAL_BYPASS                   0x01000000
MODIFY       PRM_IRQSTATUS_MPU                   0x00000000 0x00000000
WRITE        PRM_VC_VAL_BYPASS                   0x00315B12
MODIFY       PRM_VC_VAL_BYPASS                   0x01000000 0x01000000
POLL_ZERO    PRM_VC_VAL_BYPASS                   0x01000000
MODIFY       PRM_IRQSTATUS_MPU                   0x00000000 0x00000000
WRITE        PRM_VC_VAL_BYPASS                   0x00316112
MODIFY       PRM_VC_VAL_BYPASS                   0x01000000 0x01000000
POLL_ZERO    PRM_VC_VAL_BYPASS                   0x01000000
MODIFY       PRM_IRQSTATUS_MPU                   0x00000000 0x00000000
                                                 
# --- PRCM INIT ---
                                                 
WRITE        CM_SYS_CLKSEL                       0x00000007
                                                 
# Debug 
DEBUG_REG    0x0001                              0x4A31e058 0xFFFF0000 0x001B0000
DEBUG_REG    0x0002                              CONTROL_CORE_PAD_GPMC_NCS0 0x0000FFFF 0x00000003
DEBUG_REG    0x0003                              0x4A31e054 0xFFFF0000 0x001B0000
                                                 
# --- PRCM INIT DONE ---
                                                 
